Sharp PC-4741 Service Manual page 9

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--------~F~~r.------------------------------~----~------------------~-----
3-1. Memory and I/O map
3-1-1. Memory map for the PC-4700 system
FFFFFh
r - - - - - - ,
ROM-BIOS
FOOOOh \ - - - - - \
E7FFFh
EOOOOh
DOOOOh
C9FFFh
CeaaOh
BFFFFh
BBFFfh
88000h
BOFFFh
BOOOOh
9FFFFh
ooaDah
EMS window
HD ROM BIOS
System Rsvd
eGA Video Memory
System Asvd
~QA
Video Memory
Standard
Main Memory
: 640KB
20000h
Fig. 3-1 Overall memory map
3-1-2.10/MAP
Register,
Emulate~ DMA Controller
V40DMA Controller
Interrupt Controller
System Timer
PPI
NMI Mask
Asynchronous Communication (Secondary)
Hard Disk
Parallel Port
Parallel Port
VIDEO 10
VIDEO 10
VIDEO 10
VIDEO 10
FLOPPY DISK 10
Asynchronous Communication (Primary)
V40 System 10
3-2. Clock generator
: maximum 768KB
EMS
Memory
(1MB)
10 Address.
OOHnOFH
10HnlFH
20Hn3FH
40H .. 5FH
60H .. 62H
AOHnBFH
2FBHn2FFH
320Hn323H
37BH .. 37FH
3BCH .. 3BEH
3BOH .. 3BBH
3BFH
3COH .. 3CFH
3DOH .. 3DFH
3FOH .. 3F7H
3FBH .. 3FFH
FFFOH .. FFFFH
The
cloc)~
generator is
includetfin~bZ95H-1·2.-·and-~nnecte'd with-tWo"~--~
crystal oscillators of 14.3181 BMHz and 20MHz.
The two clocks pass through the clock select drcuil in LZ95H12, and
one of them is outputted from Xl terminal to V40· Xl termi,liar. ,The
details are shoWn in Fig. 3-2.
~Ji-
20MHz
CEoseD._
-
" -
~ ~ ~
-
=
CPOSC1
Clock
- X1· . X1
14.3181BMHz
select
NC'X2'
V",
OSCD
circuit
=
aSC1
Bus cycle
CPUCLK
CLKOUT
LZ95H12
generator
SYSCLK
Fig. 3-2 Overall clock generate circuit
The frequency
\If
,he clo¢k
~ypplied
from LZ95H12 Xl terminal to V40
is determined according to the states of bit 3 (OSCSPD1) and bit 2
(OSCSPDO) of the 10 port (7BH) in LZ95H12 as shown below.
7 6 5 4 3 2 0
X X X X
\x\x
107BH(RIW)
a
20MHz
Assertion of the RESET signal will reset OSCSPD [0 .. 1]. IF BOB7 is
not installed, ROM·BIOS sets OSCSPOO.
When setting OSCSPDO, the shift to frequency of 10MHz is made
wtth no !;Ittches, thus avoiding the need to reset the system.
3-3.
~eset
circuit
SCM
(LU57844)
R
ET LZ95H12
l.Z93J21
RES TCS566F
OUT ' B2C5OA V
CN7-28{34-pin slot)
CN8-49{CRT connector)
eNS·1
(HOD connector)
Fig. 3-3 Reset control circuit
The SCM can be reset in one of the following two ways.
1. When VGG turns on, a high state of signal is sent to the line ACL
of the SCM from the differentiation circuitry composed of a
capacitor and resistor.
2. When the dip switch-1.located at the lower side of the machine,
set ON, it causes the ACL input high to reset the SCM. Operation
starts when it turned off.
With depression of the ON/OFF switch while 1he machine is off or a
hardware reset is given (simultaneous depres'sion of CTRL, AL T,
SETUP keys), VCC is turned active and RESET is forced high. The
V40 synchronizes an async signal RESET with the internal clock and
sends it out as an active high signal.
The fdrmer (RESET) is sent to the V40, and the latter (RESET) to the
LZ95H12, LZ93J21, TCB566F, B2C50AV, 34'pin slot, CRT connector.
The RESET signal is inverted and sent to HDD connector.
3-4. Interrupt control
Eight maskable interrupts and one non-maskable interrupt are
provided. .
NMI is set high by the LZ95"'12 when a
sp~cific
VO
is accessed.
• Maskable interrupt may be caused in one of the following:
Numbe:r Usage Originating device
1 KeyboarQ LZ95H12
3
Asynchronous communication
(Secondary)
INSB2C50A
4
Asynchronous communication
(Primary)
5 Hard disk Hard disk controller
6 Floppy disk TCB566F
7 Parallel printer LZ93J21