Sharp PC-4741 Service Manual page 62

--------~"F~4Th@F~·----~------------------------------------------------~----------
2. Block diagram
~
.,
~SJA"
1iiS'i'!f
21
"""
= "
ro,
"""
~~,
~=
3. Pin description
-
;'~1 ' '-'; !
=
.".-
,
,..-
..,,- ...
"'"
'-'--"-'J:""" . .
~;
f----"'M ..
~
Discussed below a.re functions of
1/0
signal lines. Some of those
relate to the internal circuitrY; .
NOTE: In the discussion" low level signal means logic
0
and high
level Signal logic I,
INPUT SIGNALS
Chip select (CSO, CSt,
Cli2,
pin-12 to pin-14)
The chip .is .serected with a high state of CSO and CSI and low state
ofSC2. Chip is selected by latching the deCoded chip select signal at
a trail edge of the address strobe signal ii"[lS. When the chip is
selected, communication Is enabled between the ACE and the CPU.
Data input strobe
(DlsTFi,DisTFi,Pi~-22
and 21)
When DISIR input is ala higH orrmi'l'l'l'is at a low after the chip was
selected, statui,.jniormation Irom the ACE selected register and data
are read by the CPU.
NOTE: When eitner DISTA ocDISTA is set active; the data will be
read from the ACE to the CPU. Therefor", DisTA must be
s"lIow or DISTA lowwhen the line is notused.
Dalaoutput stfObe (DOSTI'I, OOSTR, pin-19 and 18)
When DOSTA is at a high or
DaSfi'i
is at a low after the chip was
selected, data or control word are written to thee ACE selected
register. , . -
NOTE: Either DOSTA or DOSTA must be set active to write to ACE.
Therefore, DOSTAmust be set low or
m:lSTI'i
high when the
line is
not.
uS'ed.
Address strobe (ADS, pin-25)
When this line is low, the register select signals (AO, A I, A2) and chip
select signals (CSO, CSt,
Cli2)
are latched.
NOTE: The ADS input is used when register select Signals (AO, AI,
,A2) and chip select signals (CSO, CSI,
Cli2)
are not stable.
The signal must be set low. for such this that this input is not
required. .
-60-
DLAB
A2 AI
AO,
I
'
"
Register
"
"
-
.
.
0 0 0
0
R' Receive buffer
- --'(holding register)
0 0 0 0 ,-: W Trensmitbuffer·
,
'
' .
,-.'
(holding register)
,
.
"
0 , ,0 0 1
-
,Interrupt mask .
,
~
X
0
I
0
Interrupt ID
X 0
. I
I' '
I,"
Un. control
..
X
I 0 0
Modem control l . J
. . .
X
1
0 1
' R· .. · 'Une'siaius
--_
..
.
"
X: L 1 ,0
R
. MO.dem.status .. '
. .
"
X I 1 1 Scratch pad
' , . '
1 0
0
0 ,
" Baud ratedivide register;LSB
I 0 0
i
. ,.Baud rat. divide regisier)iiSB
....
.
. ,
A: Aead only register _.,- .. ',"-- .. ,"
W: Write only register
Register select (AD, A1, At,
pin-26to
pin-28)
Used to select the register during react
or
write. _ :-: ,.,,: ".: :_, _, _ .
As shown in the table, the divisor latch .access.
bi\.<DLAB)whic~is.the
rno,st
·§igni~i9ant,pitqf"t~EilJifl~:qor:Jtr91 r~gister rel.at~.~.
tq_
r,~g.i~~~r_~_elec­
tion. In order to access the baud rate generator divisor latch, the
DLAB bH must be set I by the system s9ftware.
Master reset (MR, pin-3S)
A TTL compatible schmitt trigger buffer that has a 0.5 (siandard)
hysteresis is implemented in this input "line; When t,he line
is-
at a high
level, all registers and control logics '-are clear'ad, except for the
receiver buffer, transmit holding, and divisor latcn. Also, the output
signals (SOUT, INTAPT,
cmtf,
QOT2,
l'fi'S,
DTAI change as in
Table-I.
Receiver
clock
(RClK, pin-g)
A 16 x, clock input line that has a receiver circuit.
Serial input (SIN, pln-10)
Serial data input line from the communication link (peripheral device,
modem, data terminal).
Clear to send (CTS, piri;36)
eTS is a modem control signal whose
~tate.
is tested by referring to
the bit 4 (CTS) of the modem status register. The bit 0 (DCTS) of the
modem status register is set 1 when there was a change in the state
of the
Ci'S
input in the period that this register is r"ad after the
modem status register was read. The CTS input does not affect the
transmitter at all.
NOTE: An interrupt is caused' when the modem status interrupt is
enabled and that there was a change in the CTS bit of the
modem status register.
Data set ready (DSA, pin-37)
A low on this line indicates that the ,modem or the data set is ready to
receive and send. For DSR is a modem control input, its state can be
tested by referring to the bit 5 (DSA)of the modem status register.
The bH I (DDSA) of the modem statUs register is set I when there
was a change in the state of the
~
input in the pertod that this
register is read after the modem status register was read.
NOTE: An
in~errupt
is caw:;ed when the modem sjatus interrupt is
enabled and thanheleWas a cnangeili·tne DSR bil of the
modem status re'gister.
Data carrier detect (DCD, pin-38)
A low on this line indicates that data carrier is detected by the modem
or data set. For CD is a modem control. input, its state can be tested
by referring to the bH 7 (DCD) of the modem status register. The bit 3
(DDCD) of the modem status register is set I when there was a
change in the state of the OeD input in the period that this register is
read after the modem status register was read.
NOTE: . Ao interrupt is caused when the modem status interrupt is
enabled and that there was a change in the TICIT bit of the
modem status register.