Sharp PC-4741 Service Manual page 12

If the CPUSPD (107BH bit 1) bit is set, the bus cycle generator will
only generate slow speed memory cycles. This is done to accorn-
- mod ate
programs -uSing
softWare timing loops. Assertion
of the
RESET signal will reset CPUSPD. If CPOSPD is reset, then speed of
the cycle is dependent on the slowest device involved. If the slowest
device is a fast AD QY§ device then a fast speed cycle is generated. If
the slowest device is a fast SO bus device. then a medium speed
cycle is generated. Otherwise, a slow speed cycle is generated.
When "speed: slow" is selected in the set up menu, CPOSPD _ 1
(High)
There are two speeds for refresh cycle-fast and slow. If the EXTREF
(107BH bit 6) bit is set, the bus cycle generator will generate a slow
speed cycle. Thus DRAM on the SD bus may be refreshed. If EX-
TREF and CPUSPD are reset, then the bus cycle generator wili
generate a fast speed cycle. Thus any DRAM on the SD bus must
provide its own refresh. Resetting EXTREF may result in as much as
a 5% increase in system throughput. Assertion of the RESET signal
will reset EXTREF. When the optional EMS card (CE-453B) is in-
stalied, EXTREF = 1 (High).
7 6 5 4 3 2 0
I I
T T
3-10-2. SYSCLK Generation
For 7.16 MHz cycles, CLKOUT drives SYSCLK.
107BH
(R/W)
CPUSPD
EXTREF
For 10 MHz fast speed cycles, SYSCLK is set during T2 and is reset
during the rest of the cycle. For 10 MHz medium speed cycles,
SYSCLK is set during T2, the first TW and T 4 and is reset during the
rest of the cycle. For 10 MHz extended medium speed cycles,
SYSCLK is set during T2 and driven by CPUCLK for the rest of the
cycle. For 10 MHz slow speed cycles, SYSCLK is set during T2,
during the odd TW's and during T4 and is reset during the rest of the
cycle. There are always an even number of TW's in a 10 MHz slow
speed cycle. For 10 MHz cycles, SYSCLK is always reset during TI's
and interrupt acknowledge cycles.
3-10-3. SWRD, SMWR, SIORD and SIOWR
Generation
'S'MR15
and
~
are not asserted during non-refresh cycles that
access fast AD bus memory devices. SIORD and SIOWR are not
asserted during non-refresh cycles that access LZ95H12 internal 10
devices or V40 internal private 10 devices.
'STOFfi) and
SIOWR
are
asserted dUring accesses to emulated MDNCGA 10 addresses.
SMRD and SIOWR are not asserted during fast refresh cycles.
For 7.16 MHz cycles, the SMRD and S1OR5 signals may be reset
during T2, T3 and TW. These signals are set during the rest of the
cycle. The same is true for SMWR and SIOWR during non-refresh,
non-DMA cycles. For DMA memory write cycles, the SMWR signal
may be reset during T3 and TW.
'Si'OWR'
is set during the rest of the
cycle. For refresh and DMA memory read cycles, the
~
signal
may be reset during T3 and TW. SIOWR is set during the rest of the
cycle.
For 10 MHz fast speed cycles, the
ll1iiIFID, ~, SR5lm
and
SIOWR signals are set during the cycle. For 10 MHz medium speed
cycles, the
ll1iiIFID
and S1OR5 signals may be reset during T3 and
TW. They are set during the rest of the cycle. The same is true for
~
and
"SlOWR
during non-refresh, non-DMA cycles. For DMA
memory write cycles, the SMWR signal may be reset during ali TW's
except the first half of the first TW $Ii;1WI'i Is set during the rest of the
cycle. For refresh and DMA memory read cycles, the
"SlOWR
signal
may be reset during ali TW's except the first half of the first TW.
SIOWR is set during the rest of the cycle. For 10 MHz slow speed
cycles, the
ll1iiIFID
and
SR5lm
signals may be reset during T3 and ali
TW's except the last TW. They are set during the rest of the cycle.
The same is true for
S'KifWF1
and
'S1OWR'
during non-refresh, non-
DMA cycles. For DMA memory write cycles, the ~ signal may
-11-
-
P C-4741
be reset during all TW's except the first TW and last TW.
SMWI'!
is
set during the rest of the cycle. For refresh and DMA memory read
cycles;t11e SIOWRSIgfiliImayOe reset darlng-1!ll1"W'ln!"i<Cl!l1ptrttl1l
,01.---
first TW and last TW.
Sf'OWR
is set during the rest of the cycle.
3-10-4. READY Interpretation and RDYV40
Generation
During fast speed cycles RDYV40 Is set. RDYV40 Is set during T1
andT!.
For 7.16 MHz medium speed cycles, RDYV40 Is reset during T2 and
then READY drives RDYV40 during the rest of the cycle. For 7.16
MHz slow <peed CPU/COP memory cycles, RDYV40 is reset during
T2 and T3 and then RDYV40 Is driven by READY during the rest of
the cycle. For 7.16 MHz slow speed 10, refresh and DMA cycles,
RDYV40 Is reset during T2, T3 and the first two TW's and then
RDYV40 is driven by READY during the rest of the cycle.
For 10 MHz medium speed cycles, RDYV40 is reset during T2 and
T3 and then RDYV40 is driven by READY during the rest of the cycle.
For 10 MHz slow speed CPU/COP memory cycles, RDYV40 Is reset
during T2, T3 and the first two TW's. READY is sampled at the start
and the end of the odd TW's starting with the first TW. If READY Is
reset for either sample, then RDYV40 remains reset for two mar.
T-cycles and READY is again sampled. If READY is set for both
samples, then RDYV40 remains reset for two more T --cycles and is
then set for the rest of the cycle. For 10 MHz slow speed CPU/COP
10, refresh and DMA cycles, RDYV40 is reset during T2. T3 and the
first four TW's. READY is sampled at the start and the end of the odd
TW's starting with the third TW. If READY is reset for either sample,
then RDYV40 remains reset for two more T-cycles and READY is
again sampled. If READY is set for both samples, then RDYV40
remains reset for two more T -cycles and is then set for the rest of the
cycle.
3-10-5_ STC Generation
During fast speed cycles, STe is reset.
For 7.16 MHz medium and slow speed cycles, STe is driven by the
inverted value of
Te.
For 10 MHz medium speed cycles, STC is set during the second and
subsequent TW's and during T4 while
m
is reset. For 10 MHz slow
speed cycles, STC is set during the third and subsequent TWs and
during T 4 while Te is reset. STe Is reset during the rest of the cycle.