Sharp PC-4741 Service Manual page 52

5-3. BAU (bus arbitration unit)
is as follows:
REFU (highest priority) > DMAU > HLDRQ > CPU> REFU (lowest
priority)
The REFU can take either the highest or lowest priority depending on
the pending status of the refresh request. Even when a bus is used
by
a bus master,
if
another bus master
with
the higher priority re-
quests the bus control, the BAU requests the current bus master to
return the bus control by inactivating the acknowledge signal (i.e., bus
acknowledge signal to the CPU, DMAU, or REFU, or the HLDAK
signal to an external device). When the bus request signal (i.e., bus
request signal from the CPU, DMAU, or REFU, or the HLDRQ signal
from an external device) becomes inactive in response to this bus
relinquish request, the BAU gives the bus control to the bus master
with the higher priority.
When the bus control is sent between the internal bus masters, bus
control request, acknowledge, relinquish request, and relinquish are
efficiently performed.
5-4. CG (clock generator)
The CG generates clock signal one half the frequency of the crystal
connected across the X1 and X2 pins and provides the clock to the
CLKOUT pin and each functional block of the /17020SG. The duty
cycle of the generated clock signal is 50%.
X,
X2
I---b-,-~CLKOUT
o s c y y y y
t i t t
CLKOUT~
(CLKOUT)
Fig. 5~3 Clock generator
9-2. LU57844P SUB CPU (SCM)
1) Block diagram
zo
CLOCK
(to internal circuit)
E1
I
E2
I
-51-
5-5. REFU (refresh control unit)
-
P C-4741
nerates refresh addresses and refresh re usst signals.
By using these, the memory, if it is a dynamic
5-6. WCU (programmable wait control unit)
The WCU has a function to insert up to three clocks of wait states TW
to compensate for the process speeds of
low~speed
memories or
I/O's. The number of clocks per wait state TW can be independently
specified for CPU access, DMA access, and refresh access.
Espe~
cially, when accessing the CPU, the memory space can be divided
into three areas. These three areas and I/O can be independently
specified.
5-7. TCU (timer/counter unit)
the TCU is a timer/counter unit. Three independent counters are
provided in the TCU. The output signal of one of the counters is
supplied to internal blocks whereas that of another one is supplied to
external devices. The output of the last counter can be supplied to
both internal and external devices.
5-8. SCU (serial control unit)
The SCU performs asynchronous serial communication.
5-9. ICU (interrupt control unit)
The ICU is an interrupt control unit, and arbitrates eight interrupt
requests, generates an interrupt request that is to be sent to the CPU,
and sends the interrupt vector number to the CPU. One of the eight
interrupt request lines is not externally connected but
it
is connected
to an output of the internal timer/counter.
5-10. DMAU (DMA control unit)
The DMAU is a DMA control unit and controls data transfer performed
by using DMA (Direct Memory Access) between the memory and 1/0.