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3-17, LCD control circuit
3-17-1. 1/0 mapping "
The table beiow'shows the I/O address assignment of the MDA and
ATI(CGA).
'
I ' ,
I/O Address
Readl
Bit
Description
Write
77H
RIW
0
ATT (CGAIMDA).
1: ATI (CGA) Mode, 0: MDA
Mode _
_.
- -
4
. RWD (Reverse video)
1 ~
F:!ever$e
vi~~!l
enable
,
78H
'RJW
.
4
CURBLKO,
t
(Cilr~or BIi~k
Rate
0,1)
,
S-
,
0: Steady
,1:1/64Sblink
,','
,
'
" ,
2:
1/32
S blink
3:
1116,
S blink
6
A TIBLKO,
t.
(Attribute blink Rate
f--]
a, 1) ,
0:
Steady
1
:,1/64
S blink
,',
2: 1132
S blink
3:
1/16S
blink
Index Register
W
0
IDXO (Index Address 0)
3B4H (A TT
=0)
1
IDXl (Index Address 1)
3D4H (ATT=I)
2
IDX2 (Index Address 2)
:l
IDX3 (Index Address 3)
4
IDX4 (Index Addre .. 4) ,
5
Not used '
6
Not used
7
Not,used
Data Register
W
0
. CSSLO (Cursor Start Scan Line 0)
3B5H (ATI=O)
1
CSSL 1 (Cursor Start Scan Line 1)
3D5H (ATI=I)
2
CSSL2 (Cursor Start Scan Line 2)
{Register
3
CSSL3 (Cursor Start Scan Line 3)
Address=OAH)
4
CSSL4 (Cursor Start Scan Une 4)
5
CSSL5 (Cursor Start Scan Line 5)
6
CSSL6 (Cursor Start Scan Line 6)
7
Not used
Data Register
W
0
CESLO (Cursor End Scan Line 0)
1
CESL1 (Cursor End Scan Line 1)
3B5H (A TT =0)
2
CESL2 (Cursor End Scan Line 2)
3D5H (ATI=I)
3
CESL3 (Cursor End Scan Line 3)
(Register
4
CESL4 (Cursor End Scah Line 4)
Address=OBH)
5
CESL5 (Cursor End Scan Line 5)
6
CESL6 (Cursor End Scan Line 6)
7
Not used
Data Register
W
0
DSA8 (Display Start Address 8)
3B5H (ATI=O)
1
DSA9 (Display Start Address 9)
3D5H (ATT=I)
2
DSA 10 (Display Start Address 10)
(Register
3
DSA 1 t (Display Start Address 11)
Address=OCH)
4
DSA 12 (Display Start Address 12)
5
DSA 13 (Display Start Address 13)
6
Not used
7
Not used
Data Register
W
0
DSAO (Display Start Address 0)
3B5H(ATI=0)
1
DSA 1 (Display Start Address 1)
3D5H (ATT=I)
2
DSA2 (Display Start Address 2)
(Register
3
DSA3 (Display Start Address 3)
Address=ODH)
4
DSA4 (Display Start Address 4)
5
DSA5 (Display Start Address 5)
6
DSA6 (DiSplay Start Address 6)
1
bSA7 (Display Start Address 7)
Data Rf!!gister
RIW
a
CSA8 (Cursor Address 8)
3B5H (ATI=O)
1
csAs
(Cursor Address 9)
3D5H (ATT=I)
2
CSA 10 (Cursor Address 10)
(Register
3
csA
11 (Cursor Address 11)
Address=OEH)
4
CSA 12 (Cursor Address 12)
5
CSA 13 (Cursor Address 13)
6
Not used
7
Not used
-20-
I/O Address'
Read!
Bit
,.; Descriptiory, ,
Wrtte
Data Register
RIW
0
CSAO,(CuiSorAddr~ss
0)
SB5H (A TT =0)
1
CSA 1 (Cursor ,Address 1)
3D5H(ATI=t)
2
CSA2 (Cursor Address 2)
(Register
,
3
CSA3 (Cursor Address 3)
Address=OFH)
4
CSA4 (Cursor Address 4)
5
CSA5 (Cursor Address 5)
6
CSA6 (Cursor Address 6)
7
CSA7 (Cursor Address 7)
----
3B8H,
.. W
0,
Not used
(ATI=O)
1
Not used
2,
Not used
3
0: Video disabled, 1: Video enabled
4
Not used
5
MSB of attribute is 0: intensity,
1: blink
.,
.6 ,
Not used
,7
Not used
3D8H
W
0
0: 40 X25 Alpha, 1: 80 x 25 Alpha
(ATI=I)
1
0: Character Mode,
1: Graphics Mode
2
Nol used
3
0: Video disabled,
1: Video enabled
4
Not used
5
MSB of attribute is 0: intensity,
1: blink
6
Not used
7
Not used
3B8H
R
a
Horizontal sync
(ATI=O)
1
Not used (0 read)
2
Not used (0
re~d)
3
Blacklwhj"e video
4
Not used : ' read)
5
Not used (0 read)
6
Not used (O read)
7
Not used (0 read)
3DBH
R
a
Display enable
(ATI=I)
1
Not used (0 read)
2
Not used (0 read)
3
Vertical sync
4
Not used (1 read)
5
Not used (1 read)
6
Not used (1 read)
7
Not used (I read)
3DEH
W
0
' 640
x 200 APA 0: !wolaK alpha
pages, 1: one 32K alpha page
(ATI=I)
1
Not used
2
Not used
3
0: Select low page,
1 : select high page
4
Not used
5
Not used
6
0: underline disabled,
1: underline enabled
7
Not used
....
_.,
3-17-2. VRAM
mapping
The LCD control circuit has, ,foilr 256K-bit (64 x 4·bit) DRAM chips
which are used
for
VRAM, character 'generator table, and system
work area. A 4KB area is used as a VRAM (display buffer).in the
MDA mode, or 16KB hi th'. CGA mode, or 32KB in the ATI mode.
The A TI mode is an expanded version of the CGA ,mode which
supports
640
x 400 APA mode.
The figure next shows the display buffer memory allocation in each
mode.
The 4Kbytes monochrome
ad~ter
display buffer is mirrored into
eight different address 4Kbytes address ranges. The 16Kbytes
graphics
ad~terdisplay
buffer is mirrored into two 16Kbytes addre ..
ranges.
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