Sharp PC-4741 Service Manual page 10

3-5. Bus configuration 3-6. Memory
-
P C-4741
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________________
~~~~~~~
____________________________________ __
1) CPU (AD) bus
3-6-1. Block diagram
2) System Data (SO) bus
The bus configuration is shown in Figure 3-4.
V40
ADO-A;e0c-' -.II\~
ROM
(BIOS)
DRAMS
(640K)
--"-':; 808:
"'--"1':
(optIOn)
1-_-;l'I-'S",AO:.-=SA.:.:':,'
II
Other
,--,\It'-;==:;"\J
Devices
500-507
LZ95H12
Fig. 3-4 Bus configuration
3-6-2. LZ95H12 address assignment
RAS and CAS are generated from LZ95H12. RASO is set active if
RAS is even address or RAS1 active if RAS is odd address.
CPS signal is assigned to
C'ASl5 -
CAS4 as shown in Table 3-1.
Table 3-1
Input
A19 A1B A1l A1B AO
mAll
RASO
RAS1
CASO
X
X
X X
X
0
0 0
1
,
1 1 1
X
1 1 1 1
0 0 0
X
0
1 0 1 0
0 0
0 X
1
,
1
0
0
Neither of A19 -A17 is
X 0
,
0
1
,
"0"
X 1 1 1 0 1
-9-
v40
1
'--________ ,
ADO-AD7
64KX4X2chlp
64KX4X2chip
Fig. 3·5 RAM section block diagram
Output
GAS'
GAS2
CAS3
i;AS4 ROMCt
1 1
1 1
1
REFRESH
,
1 1 1 0 FOOOOH-FFFFFH
,
1 1
,
1 OOOOOH-1 FFFFH even
, ,
1
,
,
OOOOOH-1 FFFFH odd
0
,
1 1
1 20000H-9FFFFH even
0 1 1 1 1 20000H-9FFFFH odd