Sharp PC-4741 Service Manual page 65

I
General
!
The LZ93J21 maybe
~sed
together with a LZssH12, a V40 _",d
-optionally. The LZ93J21 incorporates the following fUnctions:
1-. system bus interface; , .
2. AEN generation;
3. serial port interlace;
4. modem port interface;:
5. parallel port adapter;-
_6. ROM disk interface; _
7. EMS
Y~rsj9n
3.2
i~t:ejface;:·
':-i
8. floppy disk adapter extension;
9. hard disk adapter interface; -
; --1 O. CRT-videa-subsystem interface;
11. LCD video subsystem;
12. fast
b~s
cYcle logic; and
13. internal/external adapter sEileCl:ibrflogic.
-LZ93J21 Block Diagram_
r·
o
_ _ _ _ • • • • _ _ _ _ _ . _ - - - - • • • • _ - - - - _ • •
REFRQIJ: AEN
OMA ackn0v.:redQe : generator
f----+-.
AEN
S[9
mlis
_L:
;'====:;-..J
System addfess bus , . _ _ ..,
S)lstam data bus
SLOeVe
Memory ItO control
-G~::;=~+===::'i->
signals
IRQ3.IRQ4
COMli2
Printer status
(Busy ACK etc)
FDT
DSKCHG
HDT
vasc
HDMEM,HQIO
L:==~==tl========::-HDWWp
r
V·RAM control signals
lCD video ( VOo-tS.VMAQ-7 )
sub system VRASO.1 VCASO., VWE
1------'-;.S.CP1.CP2
CRT video
TEST.TSTCLK
LCDUO~3.LCDL()~3
1 - - - - - - ' - ; . READY
_ ~'="=b ~,,="='m="F:!.....,
RESET
-64-
~(t93J21
signal description
No. Signal name
I/O
Descrlption,_
- - - -
1 DACKI I
,Inputto V40 charinel 0 DMA acknowledge
!
2 DACK2 I Input to V40 channell DMA acknowledge
3 DACK3 I Inputto V40 channel 2 DMAacknowledge
,
4 SMRD I Input to active low memory read signai' .. '
5
SMWR, I, Input to active. low memory write signal
6
SIORD
I' Input to
activ~
low 110 read signal
7
SIOWR I
InRYl to active_low !lO_ write.$,ignaL
8 VDO 1/0 LCO VRAM
d~ta
bus 0
9
_VD1 _
JLQ. LCD VRAM data bus 1
10 VD2 1/0 LCD VRAM data bus 2
11
VD3 !l0 LCD VRAM data bus 3
12 VD4 1/0 _LCD VRAM data bus 4
•
1_3 VD5
1/0 LCD VRAM data bys 5
'
-.
14 VD6 1/0 LCD VRAM data bus 6
15 VD7
1/0
LCD VRAM data bus 7
,
16
Vcc
+5Vsupply
17 GND OV, ground
18 VD8 1/0 LCD VRAM data bus 8
19 VD9 1/0 LCD VRAM data bus 9
20 vOla 1/0 - LCD VRAM data bus 10
21
VD11
1/0 LCD VRAMdata bus 11
22
VD12 1/0 - LCD VRAM data bus 12
23
VD13 I/O - LCD VRAM dala bus 13
24 VD14 1/0 LCD VRAM data bus 14
25 VD15 I/O LCD VRAM data bus 15
26 VMAO 0
LCD VRAM addre .. bus a
27
VMAI
0
LCD VRAMaddress bus 1
28 VMA2 0 LCD VRAM address bus 2
29
VMA3
0
LCD VRAM address bus 3
30 VMM
0
LCD VRAM address bus 4
31
VMA5 0 LCD VRAMaddress bus 5
32 VMA6
0
LCD VRAM address bus 6
33 VMA7 0 LCD VRAM address bus 7
34
TEST
I
Testpiri
35 VRASO
0
LCD VRAM a roW address
sei~Ct
signal
(active low)
36 VRAS1 0
LCD VRAM 1- row address select signal
(active low)
37 VCASO
0
LCD VRAM a column address select sig·
nal (active iow) _ ' - -
38
VCAS1 0
LCD VRAM 1 column address sE;!I,ect sig-
nal (active low)
39
VWE
0
LCD VRAM write enable signal (active low)
40
RDliilEfV!
0
Hard disk memory seleclsignal iactivei&w)
41
Fim
0
Hard disk I/O sele,ct signal (active low)
42
__ SSA'iL_
~~
~EMS
memory card system address bus j I>
43 HDLOWP 0 Not used
--'
44 HOT
r
' 1:
HD 0: FD
45 FDT I
LOW.
46
READY
0
Bus cycle ready signal •
47 SLOCYC 0 Slow bus cycle select signal
48 RESET I
Reset signal input (active high) -
49 GND
,
50
Vce
,
51
IRQ3 0 V40 channel 3 interrupt request signal
52 IRQ4 0 V40 channel 4 interrupt request signal