Denon S-301 Service Manual page 31

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No. Terminal Name
31 SYSCK
32 DV 18
DD
33 XI
34 XO
35 DV
SS
36 VDT7
37 VTD6
38 DV
SS
39 VDT5
40 VDT4
41 VDT3
42 VDT2
43 VDT1
44 VDT0
45 HDRQ
46 XHAC
47 VEFG
48 XSHD
49 DCK
50 DRVIRQ
51 DRVRST
52 DV 18
DD
53 DV 33
DD
54 DRVTX
55 DRVRX
56 DRVCLK
57 DRVRDY
58 C2PO
TE
L 13942296513
59 DADT
60 DOTX
61 LRCK
62 BCK
63 EXVCO
64 EXPLDT
65 CSL
66 SI
67 SO
68 SCLKH
69 RFOKGH
70 HFD
71 MIRRORH
72 DTC
73 AV
SS
74 ATC
75 HF
76 TLC0
77 TLC1
78 IREF
79 AV 33
DD
80 JMREF
81 JMOUT
82 CHG
83 VFBC
84 AV 18
DD
www
85 VCOI
86 LPF1
87 LPF2
88 RC
.
89 AV
SS
90 AV
SS
91 AD0
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I/O A/D Classification
O D Clock
P V & GND
DD
I D Clock
O D Clock
P V & GND
DD
O D VSTEM A/V
O D VSTEM A/V
P V & GND
DD
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
I D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM A/V
O D VSTEM Command
I D VSTEM Command
P V & GND
DD
P V & GND
DD
O D VSTEM Command
I D VSTEM Command
I D VSTEM Command
O D VSTEM Command
O D Audio I/F
O D Audio I/F
O D Audio I/F
O D Audio I/F
O D Audio I/F
I D TEST/Monitor
I D TEST/Monitor
O D ASP I/F
I D ASP I/F
O D ASP I/F
O D ASP I/F
I D ASP I/F
I D ASP I/F
I D ASP I/F
I D ASP I/F
P V & GND
DD
I A Data PLL
I A Data PLL
O A Data PLL
O A Data PLL
I A Data PLL
P V & GND
DD
I A Data PLL
O A Data PLL
I A Data PLL
I A Data PLL
P V & GND
DD
I A Data PLL
O A Data PLL
x ao
y
O A Data PLL
I A Data PLL
i
P V & GND
DD
P V & GND
DD
I A ADC
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8
Function
Clock Monitor output.
Digital 1.8V Power. (Internal logic system power)
Crystal oscillation input.
Crystal oscillation output.
Digital Ground.
MPEG data output 7.
MPEG data output 6.
Digital Ground.
MPEG data output 5.
MPEG data output 4.
MPEG data output 3.
MPEG data output 2.
MPEG data output 1.
MPEG data output 0.
MPEG data Request input.
Data Valid output.
ECC Error-sector Flag output. (L: error sector)
DVD Sector Head Flag output.
Data Strobe output.
Interrupt Request output for Host. (L: interruption is demanded)
Drive H/W Reset input. (L: reset)
Digital 1.8V power for Internal logic system.
Digital 3.3V Power for I/O.
Transmitting serial data output to Host.
Reception serial data input from Host.
Clock input from Host.
Drive Ready signal output. (L: ready)
CD-DSP C2 Pointer output.
Q Q
3 6 7 1 3
Audio serial data output.
Digital audio output.
L/R Clock output.
Audio Bit Clock output.
External Channel clock input.
External RF data input. (Logic level)
SIO for RF signal processing LSI control. Latch signal output.
SIO for RF signal processing LSI control. Serial data input.
SIO for RF signal processing LSI control. Serial data output.
SIO for RF signal processing LSI control. Serial clock output.
RF O.K. Signal input.
RF lack Signal input.
Mirror detected signal input.(H: Mirror detected)
Track cross signal input. (Logic level input)
Analog Ground.
Track Cross signal input. (Analog level input)
RF signal input.
Asymmetry Charge-pump output 0.
Asymmetry Charge-pump output 1
Reference current setting terminal for Asymmetry Circuit.
Analog 3.3V Power.
Reference current setting terminal for Jitter Monitor
Jitter Monitor output.
Reference current setting terminal for data PLL.
VCO offset frequency setting terminal for data PLL.
Analog 1.8V Power.
VCO Control voltage input terminal for data PLL.
VCO Loop-filter connection terminal 1 for data PLL.
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VCO Loop-filter connection terminal 2 for data PLL
VCO gain setting terminal for data PLL.
.
Analog Ground.
Analog Ground.
AD0 Input.
31
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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S-301
9 9
PU PD SMT
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2 8 9 9
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