National Instruments DAQ PCI-6023E User Manual page 7

Contents
Glossary
Index
Figures
Figure 1-1.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 4-14.
Figure 4-15.
Figure 4-16.
Figure 4-17.
Figure 4-18.
Figure 4-19.
Figure 4-20.
Figure 4-21.
Figure 4-22.
Figure 4-23.
Figure 4-24.
Figure 4-25.
Figure 4-26.
Figure 4-27.
PCI-6023E/6024E/6025E User Manual
The Relationship between the Programming Environment,
NI-DAQ, and Your Hardware............................................................... 1-5
PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram .................... 3-1
Dither .................................................................................................... 3-4
CONVERT* Signal Routing................................................................. 3-7
RTSI Bus Signal Connection ................................................................ 3-9
I/O Connector Pin Assignment for the PCI-6023E/PCI-6024E ........... 4-2
I/O Connector Pin Assignment for the PCI-6025E............................... 4-3
Programmable Gain Instrumentation Amplifier (PGIA) ...................... 4-10
Summary of Analog Input Connections ............................................... 4-12
Differential Input Connections for Ground-Referenced Signals .......... 4-14
Differential Input Connections for Nonreferenced Signals .................. 4-15
Single-Ended Input Connections for Nonreferenced or
Floating Signals .................................................................................... 4-18
Single-Ended Input Connections for Ground-Referenced Signals ....... 4-19
Analog Output Connections.................................................................. 4-20
Digital I/O Connections ........................................................................ 4-21
Digital I/O Connections Block Diagram............................................... 4-22
DIO Channel Configured for High DIO Power-up State
with External Load............................................................................... 4-24
Timing Specifications for Mode 1 Input Transfer ................................ 4-27
Timing Specifications for Mode 1 Output Transfer ............................. 4-28
Timing Specifications for Mode 2 Bidirectional Transfer.................... 4-29
Timing I/O Connections ....................................................................... 4-31
Typical Posttriggered Acquisition ........................................................ 4-32
Typical Pretriggered Acquisition .......................................................... 4-33
SCANCLK Signal Timing .................................................................... 4-33
EXTSTROBE* Signal Timing ............................................................. 4-34
TRIG1 Input Signal Timing.................................................................. 4-34
TRIG1 Output Signal Timing ............................................................... 4-35
TRIG2 Input Signal Timing.................................................................. 4-36
TRIG2 Output Signal Timing ............................................................... 4-36
STARTSCAN Input Signal Timing...................................................... 4-37
STARTSCAN Output Signal Timing ................................................... 4-37
CONVERT* Input Signal Timing ........................................................ 4-38
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