Figure 3-19. General-Purpose Timing Signals; Specifications - National Instruments DAQCard-1200 User Manual

Chapter 3 Signal Connections
V
IH
CLK
V
IL
V
IH
GATE
V
IL
V
OH
OUT
V
OL
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outg
t
outc
DAQCard-1200 User Manual
Figure 3-19 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the OUT output signals of
the 82C53.
t
sc
t
gsu
t
gwh
t
outg
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate

Figure 3-19. General-Purpose Timing Signals

The GATE and OUT signals in Figure 3-19 are referenced to the rising edge
of the CLK signal.
t
pwh
t
gh
380 ns min
230 ns min
150 ns min
100 ns min
50 ns min
150 ns min
100 ns min
300 ns max
400 ns max
3-30
t
pwl
t
gwl
t
outc
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