1
Pin Function
Second
No. Pin Name
Function
A
−
1
TCK
−
2
TMS
−
3
TDI
−
4
TDO
5
P2.8
EX0IN
6
P2.9
EX1IN
7
P2.10
EX2IN
8
P2.11
EX3IN
9
P2.12
EX4IN
10 P2.13
EX5IN
B
11 P2.14
EX6IN
12 P2.15
EX7IN
−
13 VSS33-1
−
14 VDD33-1
15 P4.5
CS3
16 P4.4
A20
17 P4.3
A19
18 P4.2
A18
19 P4.1
A17
−
20 VSS25-1
−
21 VDD25-1
C
22 P4.0
A16
23 A8
R8
24 A7
R7/C7
25 A9
R9
26 A6
R6/C6
27 A5
R5/C5
28 A10
R10
29 A11
R11
30 A12
R12
−
31 VSS33-2
D
−
32 VDD33-2
33 A4
R4/C4
34 A3
R3/C3
35 A2
R2/C2
36 A1
R1/C1
37 A0
R0/C0
38 A13
R13
39 A14
RAS
40 A15
CAS
−
41 VSS33-3
E
−
42 VDD33-3
−
43 MEMCLK
44 CSSDRAM −
−
45 CLKEN
−
46 CSROM
−
47 RD
−
48 UDQM
−
49 LDQM
−
50 WR
F
178
1
2
I/O
I
Clock for JTAG interface
I
Control signal for JTAG interface
I
Data input for JTAG interface
O Data output for JTAG interface
I/O General purpose I/O port/External interrupt 0
I/O General purpose I/O port/External interrupt 1
I/O General purpose I/O port/External interrupt 2
I/O General purpose I/O port/External interrupt 3
I/O General purpose I/O port/External interrupt 4
I/O General purpose I/O port/External interrupt 5
I/O General purpose I/O port/External interrupt 6
I/O General purpose I/O port/External interrupt 7
−
Digital ground for pads
−
Digital power (for pads) (3.3 V)
O General purpose output port/Chip select signal for second external static memory
O General purpose output port/Address bit
O General purpose output port/Address bit
O General purpose output port/Address bit
O General purpose output port/Address bit
−
Digital ground (for digital core)
−
Digital power (for digital core) (2.5 V)
O General purpose output port/Address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
−
Digital ground for pads
−
Digital power (for pads) (3.3 V)
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit/SDRAM address bit
O Address bit (All addresses are word addresses)/SDRAM Address bit
O Address bit/SDRAM address bit
O Address bit/Row address strobe for SDRAM access
O Address bit/Column address strobe for SDRAM access
−
Digital ground for pads
−
Digital power (for pads) (3.3 V)
O Clock for SDRAM
O Chip select signal for SDRAM device
O Enable for memory clock
O Chip select signal for ROM device
O External memory read strobe for ROM. RD is activated for every external instruction or data read access.
O Write disable for high byte
O Write disable for low byte
O Memory write strobe
PDP-R04E
2
3
Pin Function
3
4
4