Yamaha HTR-5063 Service Manual page 97

A B C
DIGITAL 5/5
1
2
1.8 1.8
1.8
1.8
3.3
1.8 1.8 0
0
3
4
0
0
0.5
0
E
0
0.3
0
0.3
0
5
0.3
0
0
3.4
1.5
1.9
0
3.4
0.9
1.9
1.2
0.7
0.4
0
1.6
0
0.3
0.4
6
0
0
0
2.4
2.4
2.4
2.4
0
0
0
0
0
0
0
0
0
7
8
IC70: ADV7800BSTZ-80
10-bit, SDTV/HDTV 3D comb filter, video decoder and graphics digitizer
POINT E XL70 (Pin 81 of IC70)
9
(CBVS+RGB)
GRAPHICS RGB
10
D E F
Page 104 C3
to VIDEO (9)_CB391
(B, G, F models)
1.8 1.8 3.4
1.8
1.8
2.9 2.9
IC73 IC74
1.8 1.8 0
0
3.3
0
VIDEO DECODER
3.4
1.8
0
IC70
1.8
0
3.3
2.7
3.1
3.2
1.6
0
3.4
0.9
0.7
0
0.8
0.7
0.9
0.8
0
0
1.7
0
0
0
0
DDR/SDR-SDRAM INTERFACE
STANDARD DEFINITION PROCESSOR (SDP)
12 10 10
ANTIALIAS
CLAMP ADC
DDR/SDR-SDRAM INTERFACE
FILTER
AIN1
TO
10 10 STANDARD
AIN12 ANTIALIAS 525p/625p MACROVISION
CLAMP ADC 54
FILTER SUPPORT DETECTION AUTODECTION
CVBS
S-VIDEO
10 10
YPrPb ANTIALIAS
CLAMP ADC
SCART- AV CODE
FILTER 2D COMB VERTICAL
INSERTION
PEAKING
10 10
ANTIALIAS
CLAMP ADC
FILTER COLORSPACE
HORIZONTAL CONVERSION
FAST BLANK
3D COMB PEAKING
OVERLAY
CONTROL
FB
CTI
TBC
LTI ITOP
CVBS OUT DAC
24
P30 TO P53
HS_IN2 CORE
DIGITAL INPUT PORT VBI DATA PROCESSOR (VDP)
VS_IN2 CLK
DVI OR HDMI COMPONENT PROCESSOR (CP)
CLK_IN
DE_IN
MACROVISION ACTIVE PEAK
SYNC PROCESSING AND
HS_IN DETECTION AND AGC
CLOCK GENERATION
VS_IN
SOG
DIGITAL
SSPD STDI COLORSPACE
SOY GAIN OFFSET AV CODE
FINE
CONVERSION CONTROL CONTROL INSERTION
CLAMP
SCLK
SCLK2
SERIAL INTERFACE
SDA
CONTROL AND VBI DATA
SDA2
ALSB
G H
Page 102 K9
to VIDEO (1)_CB305
IC72
2.7
3.2
3.3
1.8
0
1.6
1.6
0 I/P and SCALER
1.6
0
0
IC75
1.6
1.6 0
1.6
0
IC71
0
0
0
3.4
0
0
3.4
1.8
0
1.3
1.0
1.0
1.0
1.4
1.4
PIXEL DATA
IC73: R1172H181B-T1-F
P0 TO P53 IC74: R1172H331D-T1-F
Voltage regulator
Voltage regulator
CS/HS
V 4
V DD 4 5 V OUT DD
VS
FIELD/DE
Vref
Vref
SFL/SYNC_OUT
Current Limit Current Limit
CE
CE 1 2 GND 1
LLC
Pin No. Symbol Description
Pin No. Symbol
1 CE Chip Enable Pin
INT 1 CE Chip Enable Pin
2 GND Ground Pin
2 GND Ground Pin
3 NC No Connection
3 NC No Connection
4 V DD Input Pin
4 V DD Input Pin
5 V Output Pin of Voltage Regulator
OUT 5 V Output Pin of Voltage Regulator
OUT
I J K
0
0.3
0
3.4
0
0
0
0
1.7
1.7 0
0 0 3.0
3.4 0 0.3
0 0.3
1.5 0.3
1.9 3.0
0
1.9 0.3
0 1.8 3.0
1.8 3.3 0.3
0 3.4 0
0
0
3.4
0.8 0
1.7
2.6 0.3
0 3.0
0
0.3 0
0 0
0 0.3
1.7 0.3
0 3.0
3.3 0.3
3.4 0
0 0
0 0.3
0 0.3
1.7 0.3
1.7 3.0
1.6 0.3
1.5 0.3
1.4 0.3
3.3 0.3
3.4 0
BUS SWITCH
IC75: TC7WZ32FK (TE85L, F)
Dual 2-input OR gate
1A 1 8 Vcc
5 V
OUT
1B 2 7 1Y
2Y 3 6 2B
GND 4 5 2A
GND
2
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
Description ★ Components having special characteristics are marked
and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
L M N
RX-V567/HTR-5063
To DIGITAL 2/5
To DIGITAL 1/5
IC71: ABT1012Q100
Advanced video processor device
ABT1012
Video Timing
27MHz
Generator
27MHz
150MHz
(optional) Video Clock Generation
output clock
Video Out Clk
HD Scaler 12
Sync Generator
Tri-Sync
Generator Dynamic
Range
Expansion
12
12-bits in Y; 12 Scaler Bypass
12-bits in C 10
12
12 Color Space
Video Input
Conversion
CUE/
Sharpness/
12
YC Delay Test Pattern
Generator
10
10
Picture Controls 3x3 Output
3x3 Input matrix Matrix
Border Gen.
Masking Gen. 12
Panorama
12
Dynamic
Range
Input Format/ Compression
Color Space
Decoder 12
10-bits in Y; 10
10-bits in C
Input
Input Video 10 10
Bus
Output Output Video
20 Mapping
Output Format Bus
Converter Mapping
24
Processor
I2C Interface &
Control Pin to Pin Bypass
Registers
IC76-78: SN74LVTH245APW
3.3 V ABT octal bus transceivers with 3-state outputs
1 20
DIR Vcc
2 19
A1 OE
A2 3 18 B1
A3 4 17 B2
A4 5 16 B3
A5 6 15 B4
A6 7 14 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
● 印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
97