Yamaha YSP-600 Service Manual page 76

A B C
YSP-600/HTY-760
DSP 2/2
1
2
5.2
5.2
5.2 5.2
3
0.2
0
5.2
0
DIGITAL POWER AMP.
0.2
0
0.2
0
5.2
0
IC601
0.2
0
0.2
0
5.2
4
0
0.2
5.0
0
2.5
2.5
0
5
6
7
SUBWOOFER OUT
FRONT IN
SURROUND IN
8
CENTER IN
WOOFER IN
SUBWOOFER IN
9
10
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
76
D E F
5.1 5.1
5.1
5.0
5.0 5.0
3.3
0
0
0.2
0
5.0
0
0.2
0
0.2
0
5.0
0
0.2
0
0.2
0
5.0
0
0.2
5.0
0
B-1
SPEAKER OUT
2.5
0
5.0
WOOFER L OUT
D/A CONVERTER
5.1
5.1
5.1
0
0
3.3
0
0
G H I
5.1 5.1 5.1
5.0 5.0
5.0
3.3
0
0
0.2 0.2
0
0
5.0 5.0
0 0
DIGITAL POWER AMP.
0.2
0.2
0 0
0.2 0.2
0 0
5.0
5.0
0 0
IC602
0.2 0.2
0 0
0.2 0.2
0 0
5.0
5.0
0
0
0.2 0.2
5.0 5.0
0
0
2.5 2.5
2.5 0
0
5.0
No replacement part available.
サービス部品供給なし
D-AMP
10.3
3.4
1.7
1.7
0.6
1.7
IC751
1.7
0
0
CB607
Page 78 L2
to INPUT (1)_CB504
NC 1
NC 2
PVDDREG 3
AVDD 4
INLP 5
6
INLM
VREF 7
INRM 8
9
INRP
10
AVSS
PLIMIT 11
NC 12
J K L
CB601
CB602
DRIVER
TWEETER x 8
CB603
SPEAKER OUT DRIVER
TWEETER x 8
CB604
CB605
DRIVER
WOOFER L
0.1
3.3
0
0
0
0
0
0
0.1
0
3.4
3.4
3.4
3.4
CB606
DRIVER
WOOFER R
IC603: WM8728
IC751: YDA147-SZE2
Digital audio power amplifier 24-bit, 192 kHz stereo DAC
Lch
Feed Back PVDDPL
OUTPL
INLP
Gain Power PWM Level
Logic
PVSSL
Control Limit Amp Shift
INLM
OUTML
Feed Back MUTE
PVDDML
PLIMIT
GAIN0
GAIN1
SLEEPN
MUTEN
CKIN CKOUT
NCDRC0
BCKIN 3
NCDRC1 SLEEPN
Non-Clip
36 NC Oscillator MUTEN OTP
PVDDREG 3.3V MUTE
35 NC DRC OCP
Regulator Control LRCIN 1
AVDD Control
34
GAIN1 UVLO
33 GAIN0 VREF/ PROTN
VREF DIN 2
REF
32 NCDRC1
31
NCDRC0
30
CKIN
29 CKOUT
28 Feed Back PVDDPR
MUTEN MUTE
27
PROTN OUTPR
26 SLEEPN INRP
Gain Power PWM Level
Logic PVSSR
25 NC Control Limit Amp Shift
INRM
OUTMR
Feed Back
Rch PVDDMR
M N
POINT B-1 XL601 (Pin 48 of IC601)
IC601, 602: YDA141-SZ
Sound projector
Microprocessor Quarts Crystal circuit
Microprocessor interface complies with EVE.
SO is bus connected by /CS.
IRQ terminals are connected in
daisy chain, forming an OR circuit.
Chip#15 XIN XOUT Speaker A~H
WCK fs=32/44 /48k*2 DAT[15:0]
OUTPC
WCK WCK2
OUTMC
BCK LT[9:0]
TI/DSP
AMHOP
DSI[3:0]
FSHOP[1:0]
GAINA[1:0]
GAING[1:0]
DIR MCK ENABLE[7:0]
MCK=24 576MHz
Fixed SPCHK D4_core
/OCPO[7:0]
/SPERR[7:0]
/UVLC
/CKDET
8ch D4
SA_DSP /OTP
DAC & PDD Amp
/OTW
Beam & NoiseShaper
CH_A~H
MASKUVLO
MASKCKDET DAC-I,J
MASKOTP
MASKOTW
MASKOCP
TESTOTP
TESTOCP
DACENABLE[1:0]
PWMSW
/TEST
/TRIDET
DEGLITCH
EXT[0:1]
CLKC
CLKC
For DAC monitor
To be modified if there are many SDC latches
Chip#14 XIN
CLKC D4-SPJ
Bus connected to
microprocessor
Chip#0
XIN
CLKC D4-SPJ
MODE LATI2S SCKDSD SDIDEM MUTEB CSBIWL ZERO
16 20 19 18 17 15 5
8 VOUTR
VOUTL
11
12 VMID
4 10 7 14 13 9 6
MCLK AVDD DVDD VREFP VREFN AGND DGND