Yamaha YSP-600 Service Manual page 56

YSP-600/HTY-760
Pin
Function Name
No.
117 AXR0[3]
119 AXR0[4]
120 AXR0[5]/SPI1_SCS
121 AXR0[6]/SPI1_ENA
122 AXR0[7]/SPI1_CLK
126 AXR0[8]/AXR1[5]/SPI1_SOMI
127 AXR0[9]/AXR1[4]/SPI1_SIMO
130 AXR0[10]/AXR1[3]
131 AXR0[11]/AXR1[2]
134 AXR0[12]/AXR1[1]
135 AXR0[13]/AXR1[0]
137 AXR0[14]/AXR2[1]
138 AXR0[15]/AXR2[0]
139 ACLKR0
141 AFSR0
142 ACLKX0
143 AHCLKR0/AHCLKR1
144 AFSX0
105 SPIO_ENA/I2C1-SDA
107 SPIO_SCS/I2C1-SCL
108 SPIO_CLK/I2C0-SCL
110 SPIO_SIMO
111 SPIO/SOMI/I2C0-SDA
17 CLKIN
22 OSCVSS
23 OSCIN
24 OSCOUT
25 OSCVDD
27 PLLHV
14 RESET
19 TMS
21 TRST
28 TDI
29 TDO
32 EMU[0]
34 EMU[1]
35 TCK
8
16
20
33
44
53
57 CVDD
65
77
85
90
101
123
56
I/O
TYPE (1) PULL (2) GPIO (3)
I/O – Y McASP0 serial data 3
I/O – Y McASP0 serial data 4
I/O – Y McASP0 serial data 5 or SPI1 slave chip select
I/O – Y McASP0 serial data 6 or SPI1 enable (Ready)
I/O – Y McASP0 serial data 7 or SPI1 serial clock
I/O – Y McASP0 serial data 8 or McASP1 serial data 5 or SPI1 data pin slave out master in
I/O – Y McASP0 serial data 9 or McASP1 serial data 4 or SPI1 data pin slave in master out
I/O – Y McASP0 serial data 10 or McASP1 serial data 3
I/O – Y McASP0 serial data 11 or McASP1 serial data 2
I/O – Y McASP0 serial data 12 or McASP1 serial data 1
I/O – Y McASP0 serial data 13 or McASP1 serial data 0
I/O – Y McASP0 serial data 14 or McASP2 serial data 1
I/O – Y McASP0 serial data 15 or McASP2 serial data 0
I/O – Y McASP0 receive bit clock
I/O – Y McASP0 receive frame sync (L/R clock)
I/O – Y McASP0 transmit bit clock
I/O – Y McASP0 and McASP1 receive master clock
I/O – Y McASP0 transmit frame sync (L/R clock)
SPI0, I2C0 and I2C1 serial port pins
I/O – Y SPI0 enable (Ready) or I2C1 serial data
I/O – Y SPI0 slave chip select or I2C1 serial clock
I/O – Y SPI0 serial clock or I2C0 serial clock
I/O – Y SPI0 data pin slave in master out
I/O – Y SPI0 data pin slave out master in or I2C0 serial data
I – N Alternate clock input (3.3 V LVCMOS input)
PWR – N oscillator Vss tap point (for filter only)
I – N 1.2 V oscillator input
O – N 1.2 V oscillator output
PWR – N oscillator 1.2 V VDD tap point (for filter only)
PWR – N PLL 3.3 V supply input (requires external filter)
Device reset
I – N Device reset pin
Emulation/JTAG port
I IPU N Test mode select
I IPD N Test reset
I IPU N Test data in
OZ IPU N Test data out
I/O IPU N Emulation pin 0
I/O IPU N Emulation pin 1
I IPU N Test clock
Power pins
Core supply
Detail of Function
Clocks
(No connected.)