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Functional Description
EPROM
4
4-6
The MVME177 implements Flash write protection through clearing
a control bit (GPIO1) in the GPIO register in the VMEchip2, to
enable write by the software after download process/
programming is completed.
There are two 44-pin PLCC/CLCC EPROM sockets for SGS-
Thompson M27C4002 (256K x 16) or AMD 27C4096 type EPROMs.
They are organized as one 32-bit wide bank that supports:
8 bit
16 bit, and
32-bit read accesses
The EPROMs as shipped are normally used for the onboard
debugger firmware (177Bug), but could be used to download user
code to Flash. The EPROMs make up only 1MB of memory, but can
share the first 2MB of space with the first 2MB of Flash. The
EPROMs occupy only 1MB space in the ROM space in mixed mode
and will be repeated in the second 1MB space (which is reserved for
future expansion). The EPROMs could coexist with this 2MB of
Flash, or could be used to program all 4MB of Flash, then the J8
jumper could be removed to make only Flash available.
After a system reset, the EPROMs are mapped to the default
addresses $00000 through $FFFFF, and could be mapped to
$FF800000 through $FF8FFFFF if needed. The control between
mapping EPROM/Flash mixed mode and all Flash mode is done by
the combination of external board jumper J8 and the VMEchip2 bit
GPIO2. Table 4-1 shows how the ÒFlashÓ jumper and GPIO bit 2
change the EPROM/Flash configuration.
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