Motorola mobile workstation 800 series owner's manual model f5207a, f5217a (62 pages)
Summary of Contents for Motorola MVME1X7P
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MVME1X7P Single-Board Computer Programmer’s Reference Guide V1X7PA/PG1 Edition of October 2000...
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Printed in the United States of America. ® Motorola and the Motorola logo are registered trademarks of Motorola, Inc. MC68040™ and MC68060™ are trademarks of Motorola, Inc. All other products mentioned in this document are trademarks or registered trademarks of...
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
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While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
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If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
The Petra ASIC and Second-Generation MVME1X7 Boards...1-1 Features...1-3 Applicable Industry Standards...1-4 Block Diagram ...1-4 Programming Interfaces...1-7 MC680X0 MPU...1-7 Data Bus Structure ...1-7 EEPROMs on the MVME1X7P ...1-8 MVME167...1-8 MVME177...1-9 Flash Memory on the MVME177...1-9 SRAM ...1-10 Onboard SDRAM ...1-11 Battery-Backed-Up RAM and Clock...1-12 VMEbus Interface...1-12...
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Functional Description ... 1-17 VMEbus Interface and VMEchip2... 1-18 VMEchip2 General-Purpose I/O... 1-18 Petra/VMEchip2 Redundant Logic ... 1-18 Memory Maps... 1-20 Local Bus Memory Map... 1-20 Normal Address Range ... 1-20 Detailed I/O Memory Maps ... 1-25 BBRAM/TOD Clock Memory Map ... 1-41 Interrupt Acknowledge Map ...
Figure 3-1. PCCchip2 Block Diagram...3-2 Figure B-1. MVME1X7P Printer Port with MVME712M ... B-2 Figure B-2. MVME1X7P Serial Port 1 Configured as DCE ... B-3 Figure B-3. MVME1X7P Serial Port 2 Configured as DCE ... B-4 Figure B-4. MVME1X7P Serial Port 3 Configured as DCE ... B-5 Figure B-5.
Motorola VME boards which combines a variety of functions previously implemented in other ASICs (among them the MC2 chip, the IP2 chip, and the MCECC chip) in a single ASIC. On the MVME1X7P, the “Petra” chip replaces the MCECC ASIC. As of the publication date, the...
SCSI and LAN controllers. Chapter 4, MCECC (MCECC). On the MVME1X7P boards, it supplies the interface to a 144- bit wide DRAM memory system. Appendix A, Summary of accompanied the introduction of the Petra ASIC on the MVME167P and MVME177P.
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bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
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The terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls.
This chapter discusses those topics in addition to interrupt handling, the use of bus timers, and the programming interface to each device on the board. Programmable registers that reside in ASICs (Application-Specific Integrated Circuits) on the MVME1X7P boards are covered in the chapters devoted to those devices. Note The MVME1X7P’s new ’‘Petra’’...
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Programming Issues The Petra ASIC is functionally compatible with each of the components that it replaces. In cases where functionality between ASICs is exclusive, configuration switches or jumpers are provided to let you select the desired functionality. In several areas of functionality, the configuration switches provide backward compatibility with earlier MVME167/177 implementations, but you can override their settings in software if you wish.
Features The “Petra” ASIC supplants the MCECC memory controller ASIC on MVME1X7P boards, performing the memory control functions previously carried out by the MCECC chip: It supplies the programmable interface for the ECC-protected 16/32/64/128MB DRAM emulation. The following table summarizes the features of the MVME167P and MVME177P single-board computers.
Local Bus to communicate. The Local Bus is arbitrated by priority type arbiter. The priority of the Local Bus masters from highest to lowest is: Highest priority Lowest priority http://www.motorola.com/computer/literature 1-3. 82596CA LAN CD2401 serial (through the PCCchip2) 53C710 SCSI...
EEPROMs on the MVME1X7P Both boards include 44-pin PLCC/CLCC sockets for EEPROMs, organized as follows: The MVME167P boards use 27C102JK or 27C202JK type EEPROMs.
1. Map Flash and EEPROM as shown in Map 3 in Figure 1-3. 2. Copy the 177Bug into the bottom 2MB of Flash memory. 3. Remap Flash memory as shown in Map 1 in Figure 1-3. http://www.motorola.com/computer/literature Programming Interfaces Chapter 2, VMEchip2.
Programming Issues MAP 1 FFBFFFFF FLASH MEMORY FF800000 NO EPROM IN MAP Figure 1-3. MVME177 Flash and EPROM Memory Mapping Schemes SRAM The MVME167P and MVME177P single-board computers include 128KB of 32-bit wide 100ns static RAM (SRAM) that supports 8-, 16-, and 32-bit wide accesses.
MVME167P boards are built with 16MB-64MB synchronous DRAM (SDRAM). MVME177P boards are built with 16MB-128MB SDRAM. The MVME1X7P may have the SDRAM configured to model 4MB, 8MB, 16MB, 32MB, 64MB, or 128MB of ECC-protected DRAM. In addition to the onboard SDRAM, an additional mezzanine (of the type used on previous MVME1X7 boards) can be plugged in to provide up to 128MB of additional DRAM.
Programming Issues Battery-Backed-Up RAM and Clock Although the M48T58-70 RAM and clock chip is an 8-bit device, the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the M48T58. No interrupts are generated by the clock. Refer to 3, PCCchip2 guidance and battery life information.
I/O connector pinout to industry-standard connectors. Note The MVME1X7P board hardware ties the DTR signal from the CD2401 to the pin labeled RTS at connector P2. Likewise, RTS from the CD2401 is tied to DTR on P2. Therefore, when programming the CD2401, assert DTR when you want RTS, and RTS when you want DTR.
Programming Issues The CD2401 supports DMA operations to local memory. Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus. The hardware does not restrict the CD2401 to onboard DRAM.
VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus. Every MVME1X7P that is built with an Ethernet interface is assigned an Ethernet Station Address. The address is $0001AFxxxxxx where xxxxxx is the unique 6-nibble number assigned to the board (i.e., every MVME1X7P has a different value for xxxxxx).
Programming Issues SCSI Interface The MVME167P and MVME177P single-board computers provide for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.
VMEbus global timer. Refer to programming information. Functional Description This section highlights a few specific features of the MVME1X7P single- board computers. For a complete functional description of the major blocks of the MVME1X7P, refer to the Installation and Use manual.
MVME177P, follow the previous MVME177 in their routing of GPIO signals: Petra/VMEchip2 Redundant Logic In support of possible future configurations in which the MVME1X7P might be offered as a single-board computer without the VMEbus interface, certain logic in the VMEchip2 has been duplicated in the Petra chip.
ABORT VMEchip2, but with a different bit organization (refer to the VMEchip2 description in Chapter 2). In the MVME1X7P, the ABORT 7. The SRAM and EPROM decoder in the VMEchip2 (version 2) must be disabled by software before any accesses are made to these address spaces.
The following tables show the memory maps of devices that respond to the normal address range. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME1X7P, Transfer Types 0, 1, and 2 define the normal address range.
The onboard I/O space must be marked cache-inhibit and serialized in its page table. Table 1-4 on page 1-22 devices on the MVME1X7P. Table 1-3. Local Bus Memory Map Address Devices Accessed Range $00000000 - User Programmable DRAMSIZE (Onboard SDRAM)
Programming Issues 2. This area is user-programmable. The suggested use is shown in the 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. This area is not decoded. If these locations are accessed and the 6.
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TEA signal. writes: upper word first and lower word second. on the MVME1X7P. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. Computer Group Literature Center Web Site...
M48T58 BBRAM, TOD Clock BBRAM Configuration Area TOD Clock You can obtain manufacturers’ errata sheets for the various chips listed above by contacting your local Motorola sales representative. A non- disclosure agreement may be necessary. http://www.motorola.com/computer/literature Memory Maps Table 1-5...
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Programming Issues Table 1-5. VMEchip2 Memory Map (Sheet 2 of 3) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SCON FAIL FAIL FAIL AC FAIL IRQ LEVEL VME IACK IRQ LEVEL IRQ LEVEL SPARE IRQ LEVEL VECTOR BASE REGISTER 0 1-28 BGTO TIME OFF PURS...
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COUNTER 2 SCALER P ERROR IRQ LEVEL SIG 1 IRQ LEVEL IRQ LEVEL VME IRQ 4 IRQ LEVEL GPIOO This sheet begins on facing page. http://www.motorola.com/computer/literature PRESCALER TIME OUT CLOCK ADJUST SELECT OVERFLOW COUNTER 1 SPARE IRQ7 IRQ6 IRQ5 IRQ1E...
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Programming Issues Table 1-5. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Address = $FFF40100 Offsets Local -bus 1-30 Bit Numbers Chip Revision General Purpose Control and Status register 0 General Purpose Control and Status register 1 General Purpose Control and Status register 2 General Purpose Control and Status register 3 General Purpose Control and Status register 4 General Purpose Control and Status register 5...
PLTY E/L* Printer BUSY Interrupt Control Register NAME PLTY E/L* Printer Input Status Register NAME PLTY Printer Port Control Register NAME Printer Data Register NAME http://www.motorola.com/computer/literature $FFF42030 ICLR ICLR $FFF42032 ICLR $FFF42033 ICLR ICLR $FFF42036 $FFF42037 DOEN 16 bits $FFF4203A...
Programming Issues Table 1-8. MCECC Internal Register Memory Map MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name CHIP ID CHIP REVISION MEMORY CONFIG DUMMY 0 DUMMY 1 BASE ADDRESS DRAM CONTROL BCLK FREQUENCY DATA CONTROL SCRUB CONTROL SCRUB PERIOD...
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Channel Status Register Modem Signal Value Registers Local Interrupt Vector Register Interrupt Enable Register Local Interrupting Channel Register Stack Register Receive Priority Interrupt Level Register Receive Interrupt Register Receive Interrupt Status Register http://www.motorola.com/computer/literature Register Offsets Name RFAR1 RFAR2 RFAR3 RFAR4 CPSR...
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Programming Issues Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map (Continued) Base Address = $FFF45000 Register Description Receive Interrupt Status Register low Receive Interrupt Status Register high Receive FIFO Output Count Receive Data Register Receive End Of Interrupt Register Transmit Priority Interrupt Level Register Transmit Interrupt Register Transmit Interrupt Status Register...
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B Transmit Buffer Status Transmit Current Buffer Address Lower Transmit Current Buffer Address Upper Timer Period Register Receive Time-out Period Register Receive Time-out Period Regis low Receive Time-out Period Register high General Timer 1 http://www.motorola.com/computer/literature Register Offsets Name BRBCNT ARBSTS BRBSTS RCBADRL...
(TOD) clock, is defined by the chip hardware. The first area is reserved for user data. The second area is used by Motorola networking software. The third area may be used by an operating system. The fourth area is http://www.motorola.com/computer/literature...
ST = Stop Bit FT = Frequency Test x = Must be set to 0 The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows. http://www.motorola.com/computer/literature Description Mezz. Board 2 PWB Mezz. Board 2 Serial Number Reserved...
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Programming Issues struct brdi_cnfg { The fields are defined as follows: 1. Four bytes are reserved for the revision or version of this structure. 2. Twelve bytes are reserved for the serial number of the board in 3. Sixteen bytes are reserved for the board ID in ASCII format. For 4.
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14. Growth space (153 bytes) is reserved. This pads the structure to an even 256 bytes. System-specific items, such as size of system side, and systems side version, may go here. http://www.motorola.com/computer/literature 01-W3620F35C 2500 prefix. For example, for a 16MB parity mezzanine...
GCSR in the VMEbus short I/O space. 1-46 the Debugging Package User’s Manual for MVME167Bug and MVME177Bug, and the Debugging Package for Motorola 68K CISC CPUs User’s Manual) for security and data integrity of the configuration area of the NVRAM. This data is stored in hexadecimal format.
MVME177P single-board computers. The following example illustrates how to generate and handle a VMEchip2 Tick Timer 1 interrupt on M68000-based single-board computers such as the MVME1X7P. Specific values are given for the register writes. It is advisable to read this entire section before you perform any of these procedures.
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Programming Issues Step Register and Address Prescaler Control register $FFF4004C Tick Timer 1 Compare register $FFF40050 Tick Timer 1 Counter register $FFF40054 Tick Timer 1 Control register $FFF40060 (8 bits) Step Register and Address Vector Base register $FFF40088 (8 of 32 bits) Interrupt Level register 1 (bits 0-7) $FFF40078 (8 of 32 bits)
When snooping is enabled, the MC68040 MPU can source data and invalidate cache entries as required by the current cycle. The MPU cannot watch VMEbus cycles that do not access the Local Bus. Software must http://www.motorola.com/computer/literature Cache Coherency (MVME167P) Action and Reference...
Programming Issues ensure that data shared by multiple processors is kept in un-cached memory. The software must also mark all onboard I/O areas as cache inhibited and serialized. Cache Coherency (MVME177P) The MVME177P’s MC68060 processor has the ability to watch the external bus during accesses by other bus masters, maintaining coherency between the MC68060’s caches and external memory systems.To maintain cache coherency, the MC68060 provides automatic snoop-...
Once the VMEbus has been granted, a third timer takes over. This is the global VMEbus timer. This timer starts when a transfer actually begins (DS0 or DS1 goes active) and ends when that transfer completes (DS0 or http://www.motorola.com/computer/literature Measures the time an access to an onboard resource takes...
Programming Issues DS1 goes inactive). This time should be longer than any expected legitimate transfer time on the bus. We normally set it to 256 sec. This timer can also be disabled for debug purposes. Before a single-board computer access to another single-board computer can complete, however, the VMEchip2 on the accessed board must decode a slave access and request the Local Bus of the second board.
Software emulation of CAS2 and misaligned CAS instructions is performed by the MC68060 Software Package, which is included in all Motorola-supplied operating systems for the MVME177P. Contact your sales office for information about obtaining the MC68060 Software Package for use with other operating systems.
Programming Issues Sources of Local Bus Errors A TEA* signal (indicating a bus error) is returned to the Local Bus master when a Local Bus time-out occurs, a DRAM parity error occurs and parity checking is enabled, or a VME bus error occurs during a VMEbus access. The sources of Local Bus errors on the Single Board Computers are described in the next subsections.
Application software must take this possibility into account. Error Conditions This section lists the various error conditions that are reported by the single-board computer hardware. A subheading identifies each error condition; a standard format provides the following information: Description of the error...
Programming Issues MPU Parity Error Description: MPU Notification: Status: Comments: MPU Offboard Error Description: MPU Notification: Status: Comments: MPU TEA - Cause Unidentified Description: MPU Notification: Status: Comments: 1-56 A DRAM parity error. TEA is asserted during an MPU DRAM access. Bit 9 of the MPU Status and DMA Interrupt Count register in the VMEchip2 at address $FFF40048.
DMAC Parity Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature An error occurred while the MPU was attempting to access a local resource. TEA is asserted during the MPU access. Bit 7 of the MPU Status and DMA Interrupt Count register (actually in the DMAC Status register).
Programming Issues DMAC Offboard Error Description: MPU Notification: Status: Comments: DMAC LTO Error Description: MPU Notification: Status: Comments: 1-58 Error encountered while the Local Bus side of the DMAC was attempting to go to the VMEbus. DMAC interrupt (when enabled) The DLOB bit is set in the DMAC Status register (address $FFF40048 bit 4).
SCC Retry Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature An error occurred while the DMAC was Local Bus master and additional status was not provided. DMAC interrupt (when enabled) The DLBE bit is set in the DMAC Status register (address $FFF40048 bit 6).
Comments: LAN Offboard Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature Local Bus Time-out occurred while the SCC was Local Bus master. SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High...
Programming Issues LAN LTO Error Description: MPU Notification: Status: Comments: SCSI Parity Error Description: MPU Notification: Status: Comments: SCSI Offboard Error Description: MPU Notification: Status: Comments: 1-62 Local Bus Time-out occurred while the LANCE was Local Bus master. PCCchip2 Interrupt (LAN ERROR IRQ) PCCchip2 LAN Error Status register ($FFF42028) The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2.
SCSI LTO Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature Local Bus Time-out occurred while the 53C710 was Local Bus master. 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register ($FFF4202C) 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2.
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Programming Issues 1-64 Computer Group Literature Center Web Site...
Introduction This chapter describes the VMEchip2 ASIC, the local-bus/VMEbus interface chip. The VMEchip2 interfaces the local bus to the VMEbus. In addition to its VMEbus-defined functions, the VMEchip2 includes a local-bus-to- VMEbus DMA controller, VME board support features, and Global Control and Status Registers (GCSRs) for interprocessor communications.
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VMEchip2 Table 2-1. Features of the VMEchip2 ASIC (Continued) Function VMEbus-to-Local- Bus Interface 32-bit Local-Bus-to- VMEbus DMA Controller VMEbus Interrupter Features Programmable VMEbus map decoder Programmable AM decoder Programmable local bus snoop enable Simple VMEbus-to-local-bus address translation 8-bit, 16-bit and 32-bit VMEbus data width 8-bit, 16-bit and 32-bit block transfer Standard and extended VMEbus addressing Software-enabled write posting mode...
Four 16-bit dual-ported general purpose registers Interrupt Handler All interrupts level-programmable All interrupts maskable All interrupts providing a unique vector Software and external interrupts Watchdog timer Control and status bits, 4-bit counter Two tick timers Control and status bits, 32-bit counter http://www.motorola.com/computer/literature Introduction Features...
VMEchip2 Functional Blocks The following sections provide an overview of the functions implemented by the VMEchip2 ASIC. See VMEchip2. Detailed programming models for the local control and status registers (LCSRs) and the global control and status registers (GCSRs) appear in subsequent sections. Local-Bus-to-VMEbus Interface The local-bus-to-VMEbus interface allows local bus masters access to global resources on the VMEbus.
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VMEchip2 Using the four programmable map decoders, separate VMEbus maps can be created, each with its own attributes. For example, one map can be configured as A32, D32 with write posting enabled while a second map can be A24, D16 with write posting disabled. The first I/O map decoder decodes local bus addresses $FFFF0000 through $FFFFFFFF as the short I/O A16/D16 or A16/D32 area.
Requiring no external jumpers, the chip provides the means for software to program the requester to request the bus on any one of the four bus request levels, automatically establishing the bus grant daisy-chains for the three inactive levels. http://www.motorola.com/computer/literature Functional Blocks...
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VMEchip2 The requester requests the bus if any of the following conditions occur: 1. The local bus master initiates either a data transfer cycle or an 2. The chip is requested to acquire control of the VMEbus as signaled 3. The chip is requested to acquire control of the VMEbus as signaled The local-bus-to-VMEbus requester in the VMEchip2 implements a fair mode.
(in increments of 64KB), as well as setting each bank’s address modifier codes, write post enable, and snoop enable. http://www.motorola.com/computer/literature Functional Blocks A24, A32 D08(EO), D16, D32, D8/BLT,...
VMEchip2 Each map decoder includes an alternate address register and an alternate address select register. These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register. This allows the address of local resources to differ from their VMEbus address.
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VMEbus. Since the local bus is generally faster than the VMEbus, other local bus masters may use the local bus while the DMAC is waiting for the VMEbus. http://www.motorola.com/computer/literature Functional Blocks A16, A24, A32 D16, D32, D16/BLT, D32/BLT,...
VMEbus address. The DMA controller also allows DMA transfers without incrementing the local bus address, although the MVME1x7P has no onboard devices that benefit from not incrementing the local bus address. The transfer mode on the VMEbus may be D16, D16/BLT, D32, D32/BLT or D64/BLT.
Requiring no external jumpers, the chip provides the means for software to program the DMAC requester to request the bus on any one of the four bus request levels, automatically establishing the bus grant daisy-chains for the three inactive levels. http://www.motorola.com/computer/literature Functional Blocks 2-13...
VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. The requester implements a fair mode. By setting the DFAIR bit, the requester refrains from requesting the bus until it detects its assigned request line in its negated state.
When this occurs, the WDTO status bit is set; and if the local or SYSRESET function is enabled, the selected reset is generated; if the board fail function is enabled, the board fail signal is generated. http://www.motorola.com/computer/literature Functional Blocks 2-15...
VMEchip2 VMEbus Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler. The chip connects to all signals that a VMEbus interrupter is required to drive and monitor. Requiring no external jumpers, the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines.
The timeout period can be set to 8, 64, or 256 secs. The bus timer terminates an unresponded VMEbus cycle only if both it and the system controller are enabled. http://www.motorola.com/computer/literature Functional Blocks 2-17...
VMEchip2 In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time-out period. This timer can be enabled or disabled under software control. The time-out period can be programmed for 8, 64, or 256 seconds.
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The location monitor interrupters are edge-sensitive interrupters connected to the location monitor bits in the GCSR. The software 7-0 interrupters can be set by software to generate interrupts. The VMEbus IRQ7-1 interrupters are level-sensitive interrupters connected to the VMEbus IRQ7 -IRQ1 signal lines. http://www.motorola.com/computer/literature 2-19...
VMEchip2 The interrupt handler provides all logic necessary to identify and handle all local interrupts as well as VMEbus interrupts. When a local interrupt is acknowledged, a unique vector is provided by the chip. Edge-sensitive interrupters are not cleared during the interrupt acknowledge cycle and must by reset by software as required.
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W/AC This bit can be set and it is automatically cleared. This bit can 5. The state of the bit following a reset, defined as follows: Table 2-2 shows a summary of the LCSRs. http://www.motorola.com/computer/literature This bit is a read-only status bit. This bit is readable and writable. also be read.
VMEchip2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus-to-local- bus map decoders. The VMEbus-to-local-bus interface allows off-board VMEbus masters access to local on-board resources. The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders, which are part of the VMEbus-to-local-bus interface.
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A32 of the local bus and A32 of the VMEbus. In addition to the address translation method previously described, the VMEchip2 as used on the MVME1X7P includes an adder which can be used for address translation. When the adder is enabled, the local bus address is generated by adding the offset value to the VMEbus address lines VA<31..16>.
VMEchip2 $FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are disabled and the address replacement method is used following reset. Write posting is enabled for the segment by setting the write post enable bit in the attribute register.
This register is the address translation address register for the first VMEbus-to-local-bus map decoder. It should be programmed to the local bus starting address. When the adder is engaged, this register is the offset value. http://www.motorola.com/computer/literature $FFF40004 (16 bits of 32) . . . Ending Address Register 2...
VMEchip2 VMEbus Slave Address Translation Select Register 1 ADR/SIZ NAME OPER RESET This register is the address translation select register for the first VMEbus- to-local-bus map decoder. The address translation select register value is based on the segment size (the difference between the VMEbus starting and ending addresses).
VMEchip2 VMEbus Slave Write Post and Snoop Control Register 2 ADR/SIZ NAME OPER RESET This register is the slave write post and snoop control register for the second VMEbus-to-local-bus map decoder. SNP2 SNP2 ADDER2 2-32 $FFF40010 (8 bits [4 used] of 32) ADDER 0 PS When this bit is high, write posting is enabled for the...
DAT, PGM, BLK and D64; A24 and A32; and USR and SUP. At least one bit must be set from each group to enable the map decoder. http://www.motorola.com/computer/literature $FFF40010 (8 bits of 32) 0 PSL 0 PSL...
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VMEchip2 2-34 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the second map decoder does not respond to VMEbus A32 access cycles. When this bit is high, the second map decoder responds to VMEbus user (non-privileged) access cycles.
This register is the slave write post and snoop control register for the first VMEbus-to-local-bus map decoder. SNP1 SNP1 ADDER1 http://www.motorola.com/computer/literature $FFF40010 (8 bits [4 used] of 32) ADDER 0 PS When this bit is high, write posting is enabled for the address range defined by the first VMEbus slave map decoder.
VMEchip2 VMEbus Slave Address Modifier Select Register 1 ADR/SIZ NAME OPER RESET 0 PSL This register is the address modifier select register for the first VMEbus- to-local-bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64; A24 and A32; and USR and SUP. At least one bit must be set from each group to enable the first map decoder.
VMEbus address to be provided by the address translation address register rather than the upper 16 bits of the local bus. http://www.motorola.com/computer/literature When this bit is high, the first map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the first map decoder does not respond to VMEbus A32 access cycles.
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VMEchip2 Each of the four programmable local bus map decoders has a starting address, an ending address, an address modifier register with attribute bits, and an enable bit. The fourth decoder also has address translation registers. The addresses and bit definitions for these registers are in the tables below.
Local Bus Slave (VMEbus Master) Ending Address Register 1 ADR/SIZ NAME OPER RESET This register is the ending address register for the first local-bus-to- VMEbus map decoder. http://www.motorola.com/computer/literature LCSR Programming Model $FFF40014 (16 bits of 32) . . . Ending Address Register 1 0 PS 2-39...
VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 1 ADR/SIZ NAME OPER RESET This register is the starting address register for the first local-bus-to- VMEbus map decoder. Local Bus Slave (VMEbus Master) Ending Address Register 2 ADR/SIZ NAME OPER RESET This register is the ending address register for the second local-bus-to- VMEbus map decoder.
ADR/SIZ NAME OPER RESET This register is the ending address register for the fourth local-bus-to- VMEbus map decoder. http://www.motorola.com/computer/literature LCSR Programming Model $FFF4001C (16 bits of 32) . . . Ending Address Register 3 0 PS $FFF4001C (16 bits of 32) .
VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 4 ADR/SIZ NAME OPER RESET This register is the starting address register for the fourth local-bus-to- VMEbus map decoder. Local Bus Slave (VMEbus Master) Address Translation Address Register 4 ADR/SIZ NAME OPER RESET This register is the address translation address register for the fourth local-...
0 PS 0 PS This register is the attribute register for the fourth local-bus-to-VMEbus bus map decoder. http://www.motorola.com/computer/literature $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 4.
VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 3 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the third local-bus-to-VMEbus bus map decoder. 2-44 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 3.
0 PS 0 PS This register is the attribute register for the second local-bus-to-VMEbus bus map decoder. http://www.motorola.com/computer/literature $FFF40028 (8 bits of 32) O PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 2.
VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 1 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the first local-bus-to-VMEbus bus map decoder. 2-46 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 1.
$FFF4002C (8 bits of 32) . . . GCSR Group Address Register 4 $00 PS These bits are compared with VMEbus address lines A8 through A15. The recommended group address for the MVME1x7P is $D2. LCSR Programming Model 2-47...
VMEchip2 VMEbus Slave GCSR Board Address Register ADR/SIZ NAME OPER RESET This register defines the board address of the GCSR as viewed from the VMEbus. The GCSR address is defined by the group address and the board address. Once enabled, the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master.
OPER RESET This register is the map decoder enable register for the four programmable local-bus-to-VMEbus map decoders. http://www.motorola.com/computer/literature $FFF4002C (4 bits of 32) 0 PSL When this bit is high, the first local-bus-to-VMEbus map decoder is enabled. When this bit is low, the first local- bus-to-VMEbus map decoder is disabled.
VMEchip2 Local-Bus-to-VMEbus I/O Control Register ADR/SIZ NAME I2EN OPER RESET 0 PSL This register controls the VMEbus short I/O map and the F page ($F0000000 through $FF7FFFFF) I/O map. I1SU I1WP I1D16 I1EN I2PD I2SU 2-50 $FFF4002C (8 bits of 32) I2WP I2SU I2PD...
NAME SIZE OPER RESET 0 PS This function is not used on the MVME1x7P. Programming the VMEchip2 DMA Controller This section includes programming information on the DMA controller, VMEbus interrupter, MPU status register, and local-bus-to-VMEbus requester register. The VMEchip2 features a local-bus -to-VMEbus DMA controller (DMAC).
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VMEchip2 A maximum of 4GB of data may be transferred with one DMAC command. Larger transfers can be accomplished using the command chaining mode. In command chaining mode, a singly-linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands.
Address of Next Command Packet $FFF40030 (8 bits [6 used] of 32) WAIT RMW ROM0 TBLSC 0 PSL 1 PSL 0 PS These VMEchip2 bits are not used on the MVME1x7P. LCSR Programming Model Control Word SRAMS 0 PS 2-53...
Source dirty, sink byte/word/longword Source dirty, invalidate line Snoop disabled (Reserved) This bit is not used on the MVME1x7P. Its function is performed by the ROM0 bit in the Petra/MC2 PROM Access Time Control register. Refer to Chapter 3. $FFF40030 (8 bits [7 used] OF 32)
0 PS This control register is loaded by the processor; it is not modified when the DMAC loads new values from the command packet. DREQL http://www.motorola.com/computer/literature The request level is 0. The request level is 1. The request level is 2.
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VMEchip2 DRELM DFAIR DTBL DHALT 2-56 always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and re- requested at the old level.
TVME LINC VINC http://www.motorola.com/computer/literature $FFF40034 (8 bits [7 USED] of 32) VINC 0 PS 0 PS When this bit is high, the DMAC executes D16 cycles on the VMEbus.
VMEchip2 INTE DMAC Control Register 2 (bits 0-7) ADR/SIZ NAME OPER RESET This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet. Because this byte is loaded from the command packet in command chaining mode, the descriptions here also apply to the control word in the command packet.
In direct mode, this counter is programmed with the starting address of the data in local bus memory. http://www.motorola.com/computer/literature VMEbus address modifier bits 2-5, and address modifier bits 0 and 1 are provided by the DMAC to indicate a block transfer.
VMEchip2 DMAC VMEbus Address Counter ADR/SIZ NAME OPER RESET In direct mode, this counter is programmed with the starting address of the data in VMEbus memory. DMAC Byte Counter ADR/SIZ NAME OPER RESET In direct mode, this counter is programmed with the number of bytes of data to be transferred.
ADR/SIZ NAME OPER RESET This register controls the VMEbus interrupter. IRQL IRQS IRQC IRQ1S http://www.motorola.com/computer/literature $FFF40048 (8 bits [7 used] of 32) IRQ1S IRQC IRQS 0 PS 0 PS 0 PS These bits define the level of the VMEbus interrupt generated by the VMEchip2.
VMEchip2 VMEbus Interrupter Vector Register ADR/SIZ NAME OPER RESET This register controls the VMEbus interrupter vector. MPU Status and DMA Interrupt Count Register ADR/SIZ NAME OPER RESET This is the MPU status register and DMAC interrupt counter. MLOB MLPE MLBE MCLR 2-62 $FFF40048 (8 bits of 32)
This is the DMAC status register. DONE DLTO DLOB http://www.motorola.com/computer/literature The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter. The value in this counter indicates the number of commands processed when the DMAC is operated in command chaining mode.
VMEchip2 DLPE DLBE MLTO Programming the Tick and Watchdog Timers The VMEchip2 has two 32-bit tick timers and one watchdog timer. This section provides addresses and bit level descriptions of the prescaler, tick timer, watchdog timer registers, and various other timer registers. VMEbus Arbiter Time-Out Control Register ADR/SIZ NAME...
This register controls the DMAC time off timer, the DMAC time on timer, and the VMEbus global time-out timer. VGTO TIME ON TIME OFF http://www.motorola.com/computer/literature $FFF4004C (8 bits of 32) TIME ON 0 PS These bits define the VMEbus global time-out value.
VMEchip2 VME Access, Local Bus, and Watchdog Time-out Control Register ADR/SIZ NAME OPER RESET WDTO LBTO VATO 2-66 $FFF4004C (8 bits of 32) VATO LBTO 0 PS 0 PS These bits define the watchdog time-out period: Bit Encoding Time-out 1 ms 2 ms 4 ms 8 ms...
B clock divided by two. The prescaler register control logic does not allow the value 255 ($FF) to be programmed. http://www.motorola.com/computer/literature LCSR Programming Model $FFF4004C (8 bits of 32) . . .
VMEchip2 Tick Timer 1 Compare Register ADR/SIZ NAME OPER RESET The tick timer 1 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
OPER RESET This is the tick timer 2 counter. When enabled, it increments every microsecond. Software may read or write the counter at any time. http://www.motorola.com/computer/literature LCSR Programming Model $FFF40058 (32 bits) . . . Tick timer 2 Compare Register $FFF4005C (32 bits) .
VMEchip2 Board Control Register ADR/SIZ NAME OPER RESET RSWE BDFLO CPURS PURS BRFLI SFFL SCON 2-70 $FFF40060 (8 bits [7 used] of 32) SCON SFFL BRFLI PURS 1 PSL switch enable bit is used with the “no RESET VMEbus interface” option. This bit is duplicated at the same bit position in the MC2 chip at location $FFF42044.
WDEN WDRSE WDS/L WDBFE WDTO WDCC http://www.motorola.com/computer/literature $FFF40060 (8 bits of 32) WDCC WDTO WDBFE WDS/L WDRSE WDEN 0 PSL When this bit is high, the watchdog timer is enabled. When this bit is low, the watchdog timer is not enabled.
VMEchip2 WDCS SRST Tick Timer 2 Control Register ADR/SIZ NAME OPER RESET COVF 2-72 When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is cleared. When this bit is set high, a SYSRESET signal is generated on the VMEbus.
8 bits increment at the local bus clock rate and the upper 24 bits increment every microsecond. The counter may be read at any time. http://www.motorola.com/computer/literature $FFF40060 (8 bits of 32) 0 PS When this bit is high, the counter increments.
VMEchip2 Programming the Local Bus Interrupter The local bus interrupter is used by devices that need to interrupt the local bus. There are 31 devices that can interrupt the local bus through the VMEchip2. In the general case, each interrupter has a level select register, an enable bit, a status bit, a clear bit, and a set bit for the software interrupts.
VMEchip2 Local Bus Interrupter Status Register (bits 16-23) ADR/SIZ NAME OPER RESET 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
When an interrupt status bit is low, a local interrupt is not being generated. The interrupt status bits are: http://www.motorola.com/computer/literature $FFF40068 (8 bits of 32) 0 PSL 0 PSL 0 PSL Software 0 interrupt.
VMEchip2 Local Bus Interrupter Status Register (bits 0-7) ADR/SIZ NAME SPARE OPER RESET 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
VMEchip2 Local Bus Interrupter Enable Register (bits 16-23) ADR/SIZ NAME EVIA OPER RESET 0 PSL This register is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
VMEchip2 Local Bus Interrupter Enable Register (bits 0-7) ADR/SIZ NAME SPARE OPER RESET 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
0 PSL This register is used to clear the edge-sensitive interrupts. An interrupt is cleared by writing a 1 to its clear bit. The clear bits are defined below. CTIC1 CTIC2 http://www.motorola.com/computer/literature $FFF40070 (8 bits of 32) SSW5 SSW4 SSW3...
CSIG1 CSIG2 CSIG3 CDMA CVIA 2-86 Clear VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. Clear VMEbus master write post error interrupt. Clear VMEbus SYSFAIL interrupt. Not used on MVME1x7P. Clear VMEbus ACFAIL interrupt. $FFF40074 (8 bits of 32) CDMA...
$FFF40078 (8 bits [6 used] of 32) PE LEVEL 0 PSL These bits define the level of the VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. Computer Group Literature Center Web Site WPE LEVEL 0 PSL IRQ1E LEVEL 0 PSL...
This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt. DMA LEVEL These bits define the level of the DMA controller VIA LEVEL http://www.motorola.com/computer/literature $FFF40078 (8 bits [6 used] of 32) TICK2 LEVEL 0 PSL These bits define the level of the tick timer 1 interrupt.
VMEchip2 Interrupt Level Register 2 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt. SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt. SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt.
This register is used to define the level of the software 6 interrupt and the software 7 interrupt. SW6 LEVEL These bits define the level of the software 6 interrupt. SW7 LEVEL These bits define the level of the software 7 interrupt. http://www.motorola.com/computer/literature $FFF4007C (8 bits [6 used] of 32) LM1 LEVEL 0 PSL...
VMEchip2 Interrupt Level Register 3 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the software 4 interrupt and the software 5 interrupt. SW4 LEVEL These bits define the level of the software 4 interrupt. SW5 LEVEL These bits define the level of the software 5 interrupt.
SW1 LEVEL 0 PSL $FFF40084 (8 bits [6 used] of 32) SPARE LEVEL 0 PSL These bits define the level of the VMEbus IRQ7 interrupt. Not used on the MVME1x7P. LCSR Programming Model SW0 LEVEL 0 PSL VIRQ7 LEVEL 0 PSL...
VMEchip2 Interrupt Level Register 4 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the VMEbus level 5 (IRQ5) interrupt and the VMEbus level 6 (IRQ6) interrupt. The IRQ5 and IRQ6 interrupts may be mapped to any local bus interrupt level. VIRQ5 LEVEL VIRQ6 LEVEL Interrupt Level Register 4 (bits 8-15)
$FFF40088 to $67xxxxxx). This produces a Vector Base0 of $60 corresponding to the “X” in and a Vector Base1 of $70 corresponding to the “Y” in 2-4. http://www.motorola.com/computer/literature $FFF40084 (8 bits [6 used] of 32) VIRQ2 0 PSL These bits define the level of the VMEbus IRQ1 interrupt.
VMEchip2 I/O Control Register 1 ADR/SIZ NAME MIEN OPER RESET 0 PSL This register is a general purpose I/O control register. Bits 16-19 control the direction of the four General Purpose I/O pins (GPIO0-3). GPOEN0 GPOEN1 GPOEN2 GPOEN3 ABRTL ACFL SYSFL MIEN 2-96...
I/O Control Register 3 ADR/SIZ NAME GPI7 GPI6 OPER RESET This function is not used on the MVME1x7P. http://www.motorola.com/computer/literature $FFF40088 (8 bits of 32) GPIOI3 GPIOI2 GPIOI1 GPIOI0 0 PS 0 PS Connects to pin 16 of the Remote Status and Control register.
VMEchip2 Miscellaneous Control Register ADR/SIZ NAME MPIRQEN OPER RESET 0 PSL DISBGN ENINT DISBSYT 2-98 $FFF4008C (8 bits of 32) REVEROM DISSRAM DISMST NOELBBSY DISBSYT 0 PSL 0 PSL 0 PS 0 PS When this bit is high, the VMEbus BGIN filters are disabled.
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VMEchip2 is disabled. When this bit is low, the SRAM decoder in the VMEchip2 is enabled. Because the SRAM decoder in the VMEchip2 is not used on the MVME1x7P, this bit must be set. This function is not used on the MVME1x7P. This bit must not be set.
VMEchip2 GCSR Programming Model This section describes the programming model for the Global Control and Status Registers (GCSR) in the VMEchip2. The local bus map decoder for the GCSR registers is included in the VMEchip2. The local bus base address for the GCSR is $FFF40100. The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus.
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Communications between the local processor and a VMEbus master should use interrupts or mailbox locations; reset should not be used in normal communications. Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort. http://www.motorola.com/computer/literature 2-101...
VMEchip2 Programming the GCSR A complete description of the GCSR appears in the following tables. Each register definition includes a table with five lines. 1. The base address of the register and the number of bits defined in 2. The bits defined by this table. 3.
RESET This register is the VMEchip2 revision register. The revision level for the VMEchip2 starts at 0 and is incremented if mask changes are required. The VMEchip2 used on the MVME1x7P is revision $01 or greater. http://www.motorola.com/computer/literature Bit Numbers General Purpose Control and Status Register 0...
VMEchip2 VMEchip2 ID Register ADR/SIZ NAME OPER RESET This register is the VMEchip2 ID register. The ID for the VMEchip2 is 10. VMEchip2 LM/SIG Register ADR/SIZ NAME OPER RESET 1 PS This register is the VMEchip2 location monitor register and the interrupt register.
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SIG3 http://www.motorola.com/computer/literature The SIG3 bit is set when a VMEbus master writes a 1 to it. When the SIG3 bit is set, an interrupt is sent to the local bus interrupter. The SIG3 bit is cleared when the local processor writes a 1 to the SIG3 bit in this register or the CSIG3 bit in the local interrupt clear register.
VMEchip2 VMEchip2 Board Status/Control Register ADR/SIZ NAME OPER RESET 0 PSL This register is the VMEchip2 board status/control register. SYSFL SCON 2-106 Local Bus: $FFF40104/VMEbus: $XXY2 (8 bits [5 used]) SCON 0 PSL 1 PS This bit is set when the VMEchip2 is driving the SYSFAIL signal.
This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. http://www.motorola.com/computer/literature GCSR Programming Model . . . General Purpose Register 0 0 PS .
VMEchip2 General Purpose Register 3 ADR/SIZ NAME OPER RESET This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 4 ADR/SIZ NAME...
Introduction This chapter defines the peripheral channel controller ASIC, referred to hereafter as the PCCchip2. The PCCchip2 is designed to interface an MC68040-compatible local bus (Local Bus) to various peripheral devices. Summary of Major Features This section lists the major features of the PCCchip2. BBRAM interface with dynamic sizing support.
PCCchip2 Functional Description The following sections provide an overview of the functions provided by the PCCchip2. A detailed programming model for the PCCchip2 control and status registers is provided in a later section. General Description The PCCchip2 interfaces the MC68040 microprocessor bus to the local peripherals on the Single-Board Computers including: battery-backed RAM, Serial Communications Controller (CL-CD2401), LAN controller (82596CA), and SCSI controller (NCR53C710).
Word (two bytes) is mapped at $FFF46000 and the Lower Command Word (two bytes) is mapped at $FFF46002. The PCCchip2 only supports (decodes) MPU Port writes. It does not decode MPU Port reads. (Nor does the 82596CA support MPU Port reads.) http://www.motorola.com/computer/literature Functional Description...
PCCchip2 MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks. To execute an MPU Channel Attention, the Local Bus bus master performs a simple read or write to address $FFF46004. MC68040-Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel i486-bus interface.
LANC interrupts in the LANC Interrupt Control Register is higher than the level set in the Interrupt Mask Level Register). When the MPU acknowledges the LANC interrupt, the PCCchip2 responds with the vector that corresponds to LANC interrupts. http://www.motorola.com/computer/literature Functional Description...
PCCchip2 53C710 SCSI Controller Interface The PCCchip2 provides a map decoder and an interrupt handler for the NCR-53C710 SCSI I/O Processor. The base address for the 53C710 is $FFF47000. When the PCCchip2 detects low a level on the IRQ* line from the 53C710, if such interrupts are enabled, it generates an interrupt to the MPU.
SCC: auto vector and direct. In auto vector mode, the PCCchip2 supplies the interrupt vector to the MPU. (No interrupt acknowledge cycle is seen by the CD2401.) In direct mode, the SCC supplies the vector to the MPU. (The PCCchip2 passes the interrupt acknowledge cycle on through http://www.motorola.com/computer/literature Functional Description...
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PCCchip2 to the CD2401. Note that the PCCchip2 drives the CD2401 A7-A0 pins with $01 for modem interrupt acknowledges, $02 for transmit interrupt acknowledges and $03 for receive interrupt acknowledges.) The use of the auto vector mode is not recommended because the CD2401 can supply the vector and the CD2401 requires an interrupt acknowledge cycle.
An interrupt to the Local Bus is only generated if the tick timer interrupt is enabled by the Local Bus interrupter. The overflow counter can be cleared by writing a one to the overflow clear bit. http://www.motorola.com/computer/literature Functional Description...
PCCchip2 Overall Memory Map The following memory map includes all devices selected by the PCCchip2 map decoders, including those internal to the chip and those external. These devices respond only when the Transfer Type signals carry the values of %00 or %01 which correspond to Normal and MOVE16 accesses on the Local Bus.
The bit is not affected by reset. The effect of reset on this bit is variable. The bit is always 0. The bit is always 1. A summary of the PCCchip2 CSR is shown in Table 6-2. http://www.motorola.com/computer/literature Programming Model 3-11...
PCCchip2 Chip ID Register The Chip ID Register is located at $FFF42000. It is an 8-bit read-only register that is hard-wired to a hexadecimal value of $20. Writes to this register are ignored; however, the PCCchip2 always terminates the cycles properly with TA*.
The PCCchip2 runs at half the MPU speed on the MVME177P. For example, an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz. MIEN http://www.motorola.com/computer/literature $FFF42002 (8 bits) This control bit tailors the control circuit for BBRAM to the speed of BBRAM.
When the bit is cleared, EIPL<2..0> are not driven as outputs, but are inputs only. Download ROM at 0 (not applicable to MVME1X7P). This bit should remain cleared, so that DROM appears only in its normal address range. (When DR0 is set, DROM also appears at $00000000 through $0001FFFF.)
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Register, and SCC Receive Interrupt Control Register.) If this mode is disabled by setting the AVEC bits to 0, then the PCCchip2 obtains the vector from the SCC and passes it to the MPU. Using the auto vector mode is NOT recommended. http://www.motorola.com/computer/literature $FFF42003 (8 bits) 0 PL 0 PL...
PCCchip2 A suggested setting of the Local Interrupt Vector Register in the SCC chip is $5C. This produces the following vectors: Programming the Tick Timers This section provides addresses and bit level descriptions of the prescaler, tick timers, and various other timer registers. Tick Timer 1 Compare Register The Tick Timer 1 Compare Register is a 32-bit register located at $FFF42004.
The rollover time for the counter is 71.6 minutes. ADR/SIZ NAME OPER RESET http://www.motorola.com/computer/literature $FFF42008 (32 bits) . . . Tick Timer 1 Counter $FFF4200C (32 bits) . . .
PCCchip2 Tick Timer 2 Counter The Tick Timer 2 Counter is a 32-bit read/write register located at address $FFF42010. When enabled, it increments every microsecond. Software may read or write the counter at any time. ADR/SIZ NAME OPER RESET Prescaler Count Register The Prescaler Count Register is an 8-bit counter used to generate the 1 MHz clock for the two tick timers.
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If a write with the value of $FF occurs to this register, the PCCchip2 terminates the cycle properly with TA*, but the register remains unchanged. ADR/SIZ NAME OPER RESET http://www.motorola.com/computer/literature Programming Model $FFF42015 (8 bits) . . . Prescaler Clock Adjust $DF P 3-21...
PCCchip2 Tick Timer 2 Control Register This is an 8-bit read/write register that controls Tick Timer 2. It is located at address $FFF42016. ADR/SIZ NAME OVF3 OPER RESET 0 PL COVF OVF3-OVF0 These four bits are the outputs of the overflow counter. 3-22 $FFF42016 (8 bits) OVF2...
OVF2 OPER RESET 0 PL 0 PL COVF OVF3-OVF0 These four bits are the outputs of the overflow counter. http://www.motorola.com/computer/literature $FFF42017 (8 bits) OVF1 OVF0 0 PL 0 PL Counter Enable. When this bit is high, the counter increments. When this bit is low, the counter does not increment.
OPER RESET IL2-IL0 ICLR http://www.motorola.com/computer/literature $FFF42019 (8 bits) When GPO is set, and GPOE is set, the GPIO pin is at a logic high level. When GPO is cleared, and GPOE is set, the GPIO pin is at a logic low level.
PCCchip2 Tick Timer 1 Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 ICLR 3-26 Interrupt Status. When this bit is high a Tick Timer 2 interrupt is being generated at the level programmed in IL2-IL0 (if nonzero). This bit is edge-sensitive and can be cleared by writing a logic 1 into the ICLR control bit.
ADR/SIZ NAME OPER RESET SCLR LTO,EXT, PRTY,RTRY error condition encountered by the SCC while performing http://www.motorola.com/computer/literature $FFF4201C (8 bits) RTRY PRTY 0 PL 0 PL Writing a 1 to this bit clears bits 25 through 28 (LTO, EXT, PRTY, and RTRY). Reading this bit always yields These bits indicate the status of the last Local Bus DMA accesses to the Local Bus.
PCCchip2 SCC Modem Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 AVEC 3-28 $FFF4201D (8 bits) AVEC 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC modem Interrupt. Level 0 does not generate an interrupt. When this bit is high, the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC modem interrupt.
SCC Transmit Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 AVEC http://www.motorola.com/computer/literature $FFF4201E (8 bits) AVEC 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC Transmit Interrupt. Level 0 does not generate an interrupt.
PCCchip2 SCC Receive Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 AVEC SC1-SC0 Note 3-30 $FFF4201F (8 bits) AVEC 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC Receive Interrupt. Level 0 does not generate an interrupt.
Note If this register is read when an interrupt is not present, the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled. MIV7-MIV0 http://www.motorola.com/computer/literature $FFF42023 (8 bits) MIV5 MIV4 MIV3 Modem interrupt vector bits 7-0 reflect the modem interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle.
PCCchip2 Transmit PIACK Register ADR/SIZ NAME TIV7 OPER RESET The Transmit PIACK Register is used to execute transmit pseudo interrupt acknowledge cycles to the CD2401. When the Local Bus master initiates a read cycle to this register, the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with A7-A0 = $02.
Note If this register is read when an interrupt is not present, the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled. RIV7-RIV0 http://www.motorola.com/computer/literature $FFF42027 (8 bits) RIV5 RIV4 RIV3 Receive Interrupt vector bits 7-0 reflect the transmit interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle.
PCCchip2 LANC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the LANC interrupt control registers and status register. LANC Error Status Register ADR/SIZ NAME OPER RESET SCLR LTO,EXT,PRTY 3-34 $FFF42028 (8 bits) PRTY 0 PL Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY).
PCCchip2 LANC Bus Error Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 ICLR SC1-SC0 Note 3-36 $FFF4202B (8 bits) ICLR 0 PL 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level. Level 0 does not generate an interrupt. Writing a logic 1 into this bit clears the INT status bit.
ADR/SIZ NAME OPER RESET SCLR LTO,EXT,PRTY http://www.motorola.com/computer/literature $FFF4202C (8 bits) PRTY 0 PL Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY). Reading this bit always yields 0. These bits indicate the status of the last Local Bus error condition encountered by the SCSI processor while performing DMA accesses to the Local Bus.
PCCchip2 SCSI Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 3-38 $FFF4202F (8 bits) 0 PL 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for the SCSI Processor. Level 0 does not generate an interrupt.
OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF42032 (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer SEL. Level 0 does not generate an interrupt. In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF42034 (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer BUSY. Level 0 does not generate an interrupt. In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
PCCchip2 Printer Input Status Register ADR/SIZ NAME PINT OPER RESET PINT 3-44 $FFF42036 (8 bits) This bit reflects the state of the Printer Busy input pin. It is 1 when BSY is high and 0 when BSY is low. This bit reflects the state of the Printer Paper Error input pin.
FAST Note The PCCchip2 runs at half the MPU speed on the MVME177P. For example, an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz. http://www.motorola.com/computer/literature $FFF42037 (8 bits) DOEN 0 PL 0 PL Manual Strobe Control - This bit selects the auto or manual mode for the printer strobe.
PCCchip2 DOEN Chip Speed Register ADR/SIZ NAME OPER RESET CS31-CS16 3-46 Printer Input Prime - This bit controls the input prime signal. When this bit is high, the input prime signal is activated. When this bit is low, the input prime signal is not activated.
Printer Data Register ADR/SIZ NAME OPER RESET PD15-PD0 http://www.motorola.com/computer/literature $FFF4203A (16-bits) 15-0 PD15 - PD0 Writing to these bits causes the PCCchip2 to latch data into the external printer data buffer. Generally the printer data buffer only connects to PD7-PD0, because most printer data paths are 8 bits wide.
PCCchip2 Interrupt Priority Level Register ADR/SIZ NAME OPER RESET IPL2-IPL0 3-48 $FFF4203E (8 bits) Interrupt Priority Level - These bits reflect the priority- encoded interrupt request level. This level is a combination of the PCCchip2 interrupt requests and the interrupt requests driven onto the EIPL2-EIPL0 pins. Note that when the C040 bit is cleared, external devices can drive EIPL2-EIPL0 with their interrupt requests.
OPER RESET MSK2-MSK0 Interrupt Mask Level - The interrupt mask level bits MSK2 http://www.motorola.com/computer/literature $FFF4203F (8 bits) determine the level which must be exceeded by IPL2- IPL0 in order for the PCCchip2 to assert its INT pin. The MSK bits are encoded as follows:...
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PCCchip2 3-50 Computer Group Literature Center Web Site...
4MCECC Functions Introduction The ECC DRAM Controller ASIC (MCECC) is a device used on earlier MVME167/177 models whose functions are now incorporated into the Petra chip on the MVME1x7. The two memory controllers modeled in Petra duplicate the functionality of the “parity memory controller” found in MC ASICs as well as that of the “single-bit error correcting/double-bit error detecting”...
MCECC Functions Features MCECC functions now implemented on the Petra chip include: Table 4-1. MCECC Functions on the Petra ASIC Function Memory Control 2-1-1-1 memory accesses (sustained) for burst writes 4-1-1-1 memory accesses (sustained) for burst reads (5-1-1-1 with BERR on or when FSTRD is cleared) Support for byte, two-byte, four-byte, and cache line read or write transfers Programmable base address for DRAM...
The Petra MCECC sector design is targeted for SDRAM devices of the PC100 type. Memory access time are not influenced by the settings of mode bits or SDRAM speed selections. The basic performance specifications for the MCECC sector are listed in Table 4-2. http://www.motorola.com/computer/literature Functional Description...
MCECC Functions Note Table 4-2. Memory System Cycle Timing Access Description Read Single Read Burst Write Burst Write Longword Write 1 or 2 Bytes 9 clock cycles Cache Coherency The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle.
3. Terminate the cycle normally. (Assert TA to the local bus.) 4. Log the error if not already logged. 5. Notify the local MPU via interrupt, if so enabled. http://www.motorola.com/computer/literature Functional Description...
MCECC Functions Double Bit Error (Cycle Type = Burst Read or Non-Burst Read) You cannot correct the data that is driven to the local MC680x0 bus. 1. Leave the error in DRAM. (Note that the error is not corrected in 2.
Triple (or Greater) Bit Error (Cycle Type = Scrub) Some of these errors are detected correctly and are treated the same as a double-bit error. The rest may show up as "no error" or "single-bit error", both of which are incorrect. http://www.motorola.com/computer/literature Functional Description...
MCECC Functions Error Logging ECC error logging is facilitated by the Petra MCECC sector because of its internal latches. When an error (single- or double-bit) occurs in the DRAMs to which the MCECC sector is connected, it freezes the address of the error and the syndrome bits associated with the data that is in error.
Software can override this initial setting by writing to the Defaults registers. However, it is not recommended that non-test software alter the contents of the Defaults registers. The actual values loaded into the Defaults registers are determined by board-level jumpers and configuration resistors. http://www.motorola.com/computer/literature Functional Description...
MCECC Functions Programming Model This section defines the programming model for the control and status registers (CSRs) in the MCECC sector. The base address of the CSRs is hard-coded to the address $FFF43000 for the MCECC sector on the first mezzanine board and to $FFF43100 for the MCECC sector on the second mezzanine board.
Petra/MCECC ASIC. The current value of the register is $01. Although writes to this register are ignored, the MCECC sector pair always terminates the cycles properly with TA . ADR/SIZ 1st $FFF43004/2nd $FFF43104 (8-bits) NAME REV7 REV6 OPER RESET http://www.motorola.com/computer/literature CID5 CID4 CID3 CID2 REV5 REV4 REV3 REV2 Programming Model...
DRAM configurations from earlier programming models. For the actual SDRAM device and size options now applicable to the MVME1x7P boards, refer to FSTRD reflects the state of the FSTRD bit in Defaults Register 1. When 1, this bit indicates that DRAM reads are operating at full speed.
MCECC Functions NCEBEN Setting the NCEBEN control bit enables the MCECC pair NCEIEN When NCEIEN is set, the logging of a non-correctable RWB3 RWB4 RWB5 BAD22, BAD23 BCLK Frequency Register The Bus Clock (BCLK) Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz (i.e., $19 for 25MHz and $21 for 33MHz).
NAME BCK7 BCK6 OPER RESET Data Control Register ADR/SIZ 1st $FFF43020/2nd $FFF43120 (16-bits) NAME OPER RESET RWCKB http://www.motorola.com/computer/literature BCK5 BCK4 BCK3 BCK2 DERC ZFILL RWCKB 1 PLS 0 PLS 0 PLS READ/WRITE CHECKBITS, when set, enables the data from the seven checkbits in the Petra MCECC sector (bits 30-24) to be written and read on the local MC680x0 data bus.
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MCECC Functions 1. Stop all scrub operations by clearing all of the STON bits and setting 2. Set the DERC and RWCKB bits in the Data Control register. 3. Perform the desired read and/or write checkbit operations. 4. Clear the DERC and RWCKB bits in the Data Control register. 5.
0 PLS RWB0 SBEIEN SCRBEN This control bit enables the scrubber to operate. When http://www.motorola.com/computer/literature cleared during normal system operation. DERC also allows the write portion of a read-modify-write to complete regardless of whether or not there was a multiple bit error during the read portion of the read-modify-write.
MCECC Functions SCRB Scrub Period Register Bits 15-8 The Scrub Period Control register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control register. The time between scrubs is approximately two seconds times the value programmed into the Scrub Period register.
Scrub Time On/Time Off Register ADR/SIZ 1st $FFF43034/2nd $FFF43134 (8-bits) NAME RWB7 STON2 OPER RESET 0 PLS 0 PLS STOFF2-STOFF0 http://www.motorola.com/computer/literature CPS57 CPS4 CPS3 CPS2 STON1 STON0 STOFF2 0 PLS 0 PLS 0 PLS STOFF2-STOFF0 control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub.
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MCECC Functions STOFF2 STOFF1 STON2-STON0 STON2 STON1 4-22 STOFF0 Scrubber Time Off Request DRAM immediately Request DRAM after 16 BCLK cycles Request DRAM after 32 BCLK cycles Request DRAM after 64 BCLK cycles Request DRAM after 128 BCLK cycles Request DRAM after 256 BCLK cycles Request DRAM after 512 BCLK cycles Request DRAM never STON2-STON0 control the amount of time that the...
OPER RESET 0 PLS 0 PLS http://www.motorola.com/computer/literature Note that if STON2-0 is zero, the scrubber always releases the DRAM after one memory cycle, even if neither the local bus nor refresher need it. Read/Write Bit 7 is a general-purpose read/write bit.
MCECC Functions Scrub Prescaler Counter (Bits 7-0) This register reflects the current value in the scrub prescaler bits 7-0. ADR/SIZ NAME SPS7 OPER RESET 0 PLS Scrub Timer Counter (Bits 15-8) This read/write register is the Scrub Timer counter. If scrubbing is enabled and the Scrub Period register is non-zero, the Scrub Timer counter increments approximately once every two seconds until it matches the value programmed into the Scrub Period register, at which time it clears...
This register reflects the current value in the Scrub Address counter bits 26-24. ADR/SIZ 1st $FFF4304C/2nd $FFF4314C (8-bits) NAME OPER RESET http://www.motorola.com/computer/literature 0 PLS 0 PLS 0 PLS 0 PLS SAC26 0 PLS Programming Model...
MCECC Functions Scrub Address Counter (Bits 23-16) This register reflects the current value in the Scrub Address counter bits 23-16. ADR/SIZ NAME SAC23 OPER RESET 0 PLS Scrub Address Counter (Bits 15-8) This register reflects the current value in the Scrub Address counter bits 15-8.
ERRLOG OPER RESET 0 PLS 0 PLS EALT ESCRB http://www.motorola.com/computer/literature ESCRB EALT 0 PLS 0 PLS 0 PLS SINGLE BIT ERROR is set when the last error logged was due to a single-bit error. It is cleared when a 1 is written to the ERRLOG bit.
MCECC Functions ERRLOG When set, ERRLOG indicates that a single- or a double- Error Address (Bits 31-24) This register reflects the value that was on bits 31-24 of the local MC680x0 address bus at the last logging of an error. ADR/SIZ NAME EA31...
This register reflects the value that was on bits 7-4 of the local MC680x0 bus at the last logging of an error. ADR/SIZ 1st $FFF4306C/2nd $FFF4316C (8-bits) NAME OPER RESET 0 PLS 0 PLS http://www.motorola.com/computer/literature EA13 EA12 EA11 EA10 0 PLS 0 PLS 0 PLS 0 PLS...
MCECC Functions Error Syndrome Register ADR/SIZ NAME OPER RESET 0 PLS S6-S0 Defaults Register 1 ADR/SIZ NAME RWB7 OPER RESET 0 PL It is not recommended that non-test software write to this register. RSIZ2-RSIZ0 4-30 1st $FFF43070/2nd $FFF43170 (16-bits) 0 PLS 0 PLS 0 PLS 0 PLS...
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RSIZ2 RSIZ1 SELI1, SELI0 SELI1 FSTRD http://www.motorola.com/computer/literature RSIZ0 DRAM Array Size 16MB 32MB 64MB 128MB Reserved Reserved The states of RSIZ2-0 after reset (power-up, soft, or local) match those of the RSIZ2-0 bits from the reset serial bit stream. The SELI1, SELI0 control bits determine the base address...
MCECC Functions RWB6 RWB7 Defaults Register 2 ADR/SIZ NAME 0 OPER R/W RESET 0 PLS It is not recommended that non-test software write to this register. RESST2-RESST0 4-32 being set. The state of FSTRD after a reset (power-up, soft, or local) is determined by board-level configuration resistors.
1st $FFF4307c/2nd $FFF4317c (8-bits) NAME OPER RESET 0 PLS 0 PLS SDCFG2-SDCFG0 SDCFG2 SDCFG1 http://www.motorola.com/computer/literature SDCFG2 SDCFG1 SDCGF0 0 PLS V PLS V PLS V PLS Define the physical SDRAM memory population on the printed circuit board: SDCFG0 DRAM Array Size...
MCECC Functions Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational. The MCECC does not perform this initialization automatically, but depends on software to perform enough dummy accesses to DRAM to meet the requirement.
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11. Clear the ZFILL bit in the MCECC pair. (Clear Bit 28 of offset $20.) 12. The entire DRAM that is controlled by this MCECC is now zero- filled. The software can now program the appropriate scrubbing mode and other desired initialization, and enable DRAM for operation. http://www.motorola.com/computer/literature Programming Model 4-35...
MCECC Functions Syndrome Decoding The following table defines the syndrome bit encoding for the Petra/MCECC ASIC. A syndrome code value of $00 indicates no error found. All other syndrome code values denote an error. The bit in error is decoded as shown in the table. Bit in Error Bit 0 Bit 1...
SDRAM configuration, the following table relates bits in the Error Address register to the physical bank where the error originated. Table 4-5. Identifying SDRAM Bank in Error SDCFG2 SDCFG1 http://www.motorola.com/computer/literature DRAM Array Size and Bank with SDCFG0 the Error Device is 64Mbit x 16 data with one bank composed of 3 devices.
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MCECC Functions 4-38 Computer Group Literature Center Web Site...
Petra ASIC on the MVME167P and MVME177P single-board computers. Differences in function and implementation between previous MVME167 and MVME177 models and the new MVME1x7P boards are listed in the following table.. Function MCECC memory control MCECC ASIC, revision 00.
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Summary of Changes Computer Group Literature Center Web Site...
Introduction This appendix has connection diagrams for the printer port and the four serial ports on the MVME1X7P. These ports are connected to external devices through an MVME712M transition module. The configuration of the serial ports as Data Terminal Equipment (DTE) or Data Circuit-terminating Equipment (DCE) is accomplished by jumpers on the transition module.
CRelated Documentation MCG Documents The Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or electronic copies of MCG publications by: Contacting your local Motorola sales office Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature...
M68000 Family Reference Manual MC68060 Microprocessor User’s Manual Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com Web: http://www.mot.com/SPS...
NOTE: An earlier version of the VME specification is available as: Versatile Backplane Bus: VMEbus Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 http://www.motorola.com/computer/literature Related Specifications Publication Number Z85230pb.pdf Publication Number...
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Related Documentation Table C-3. Related Specifications (Continued) Microprocessor system bus for 1 to 4 byte data Bureau Central de la Commission Electrotechnique Internationale 3, rue de Varembé Geneva, Switzerland ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131- 198X, Revision 10c Global Engineering Documents 15 Inverness Way East Englewood, CO 80112-5704...
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MVME167Bug/177Bug debugging packages 1-52 MVME1X7P example of VMEchip2 Tick Timer 1 features functional description 1-42 microprocessors 1-41 MVME712M, MVME1X7P printer port no-address-increment DMA transfers 1-46 non-burst read cycle type non-burst write cycle type Computer Group Literature Center Web Site Index 1-42 1-34...
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3-18 SCC Error Status register and Interrupt Control registers 3-27 SCSI controller interface tick timer support 1-16, http://www.motorola.com/computer/literature Vector Base register periodic interrupt example periodic interrupts (PCCchip2 ASIC) Petra ASIC functionality of redundancies with VMEchip2 PIACK register, modem...
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Printer Input Status register (PCCchip2 ASIC) 3-44 Printer PE Interrupt Control register (PCCchip2 ASIC) printer port connection MVME1X7P, MVME712M B-2, B-3, B-4, B-5, B-6, B-7, B-8, B-9, B-10 printer port connection diagrams Printer Port Control register (PCCchip2 ASIC) 3-45 Printer SEL Interrupt Control register...
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VMEbus segment 2-30, 2-31 slave map decoders, VMEbus 2-26 snoop control SCC receive 3-30 http://www.motorola.com/computer/literature snoop control bits snoop control register snoop control, LANC bus error snoop function enabling 2-28, 2-32, snoop signal lines (DMAC) snooping, definition of 1-49,...