Nations N32L43 Series Manuals

Manuals and User Guides for Nations N32L43 Series. We have 1 Nations N32L43 Series manual available for free PDF download: User Manual

Nations N32L43 Series User Manual

Nations N32L43 Series User Manual (698 pages)

32-bit ARM Cortex-M4F microcontroller

Brand: Nations | Category: Microcontrollers | Size: 13 MB

Table of Contents

Table of Contents
2
Abbreviations in the Text
25
Describes the List of Abbreviations Used in the Register Table
25
Available Peripherals
25
Memory and Bus Architecture
26
System Architecture
26
Bus Architecture
26
Figure 2-1 Bus Architecture
26
Bus Address Mapping
27
Table 2-1 List of Peripheral Register Addresses
28
Figure 2-2 Bus Address Map
28
Bit Banding
30
Boot Management
30
Boot Configuration
31
Table 2-2 List of Boot Mode
31
Embedded Boot Loader
32
Memory System
32
FLASH Specification
32
Table 2-3 Flash Bus Address List
32
Option Byte
36
Table 2-4 Option Byte List
37
Write Protect
38
Read Protection
38
Table 2-5 Read Protection Configuration List
39
Table 2-6 Flash Read-Write-Erase (1) Permission Control Table
40
Icache
44
Software Interface
44
Sram
46
FLASH Register Description
46
Table 2-7 FLASH Register Overview
46
Power Control (PWR)
56
General Description
56
Power Supply
56
Power Supply Supervisor
57
Figure 3-1 Power Supply Block Diagram
57
Figure 3-2 Brown-Out Reset (BOR) Waveform
58
Programmable Voltage Detector (PVD)
58
Power Modes
59
Table 3-1 Power Modes
59
Figure 3-3 PVD Threshold Waveform
59
Table 3-2 Blocks Running State
60
RUN Mode
61
SLEEP Mode
62
Enter SLEEP Mode
62
Exit SLEEP Mode
63
LOW POWER RUN Mode
63
LOW POWER SLEEP Mode
64
STOP2 Mode
64
STANDBY Mode
65
Enter STANDBY Mode
65
Exit STANDBY Mode
66
Low-Power Auto-Wakeup (AWU) Mode
66
PWR Registers
67
PWR Register Overview
67
Power Control Register 1 (PWR_CTRL1)
67
Table 3-3 PWR Register Overview
67
Power Control Register 2 (PWR_CTRL2)
68
Power Control Register 3 (PWR_CTRL3)
69
Power Status Register 1 (PWR_STS1)
71
Power Status Register 1 (PWR_STS1)
72
Power Status Clear Register (PWR_STSCLR)
73
Reset and Clock Control (RCC)
74
Reset Control Unit
74
Power Reset
74
System Reset
74
Software Reset
75
Low-Power Management Reset
75
Low Power Domain Reset
75
Clock Control Unit
75
Figure 4-1 System Reset Generation
75
Clock Tree Diagram
77
HSE Clock
77
Figure 4-2 Clock Tree
77
External Crystal/Ceramic Resonator (HSE Crystal)
78
HSI Clock
78
Figure 4-3 HSE/LSE Clock Source
78
MSI Clock
79
PLL Clock
79
LSE Clock
80
LSI Clock
80
Figure 4-4 PLL Clock Source Selection
80
System Clock (SYSCLK) Selection
81
Clock Security System (CLKSS)
81
LSE Clock Security System (LSECSS)
82
RTC Clock
82
Watchdog Clock
82
Clock Output(MCO)
82
RCC Registers
83
RCC Register Overview
83
Table 4-1 RCC Register Overview
83
Clock Control Register (RCC_CTRL)
84
Clock Configuration Register (RCC_CFG)
86
Clock Interrupt Register (RCC_CLKINT)
90
APB2 Peripheral Reset Register (RCC_APB2PRST)
93
APB1 Peripheral Reset Register (RCC_APB1PRST)
94
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)
97
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)
98
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)
99
LOW POWER Domain Control Register (RCC_LDCTRL)
102
Clock Control/Status Register (RCC_CTRLSTS)
103
AHB Peripheral Reset Register (RCC_AHBPRST)
106
Clock Configuration Register 2 (RCC_CFG2)
106
Clock Configuration Register 3 (RCC_CFG3)
108
Retention Domain Control Register (RCC_RDCTRL)
109
PLL and HSI Configuration Register (RCC_PLLHSIPRE)
111
SRAM Control/Status Register (RCC_SRAM_CTRLSTS)
111
GPIO and AFIO
113
Summary
113
I/O Function Description
114
I/O Mode Configuration
114
Table 5-1 I/O Port Configuration Table
114
Figure 5-1 Basic Structure of I/O Port
114
Table 5-2 Input and Output Characteristics of Different Configurations
115
Figure 5-2 Input Floating/Pull-Up/Pull-Down Configuration
116
Figure 5-3 Output Mode Configuration
117
Analog Mode
118
Figure 5-4 Alternate Function Configuration
118
Status after Reset
119
Figure 5-5 High Impedance Analog Mode Configuration
119
Individual Bit Setting and Bit Clearing
120
External Interrupt/Wake-Up Line
120
Alternate Function
120
JTAG/SWD Alternate Function Remapping
121
Table 5-3 Debug Port Image
121
Table 5-4 ADC External Trigger Injection Conversion Alternate Function Remapping
121
Table 5-5 ADC External Trigger Regular Conversion Alternate Function Remapping
122
Table 5-6 TIM1 Alternate Function Remapping
122
Table 5-7 TIM2 Alternate Function Remapping
122
Table 5-8 TIM3 Alternate Function Remapping
123
Table 5-9 TIM4 Alternate Function Remapping
123
Table 5-10 TIM5 Alternate Function Remapping
123
Table 5-11 TIM8 Alternate Function Remapping
123
Table 5-12 TIM9 Alternate Function Remapping
124
Table 5-13 LPTIM Alternate Function Remapping
124
Table 5-14 CAN Alternate Function Remapping
124
Table 5-15 USART1 Alternate Function Remapping
125
Table 5-16 USART2 Alternate Function Remapping
125
Table 5-17 USART3 Alternate Function Remapping
125
Table 5-18 UART4 Alternate Function Remapping
126
Table 5-19 UART5 Alternate Function Remapping
126
Table 5-20 LPUART Alternate Function Remapping
126
Table 5-21 I2C1 Alternate Function Remapping
127
Table 5-22 I2C2 Alternate Function Remapping
128
Table 5-23 SPI1 Alternate Function Remapping
128
Table 5-24 SPI2/I2S2 Alternate Function Remapping
129
Table 5-25 COMP1 Alternate Function Remapping
129
Table 5-26 COMP2 Alternate Function Remapping
129
Table 5-27 EVENTOUT Alternate Function Remapping
130
Table 5-28 RTC Alternate Function Remapping
130
Table 5-29 LCD Alternate Function Remapping
130
I/O Configuration of Peripherals
131
Table 5-30 LCD Pin Mapping Function Distinction
131
Table 5-31 ADC/DAC
131
Table 5-32 TIM1/TIM8
132
Table 5-33 TIM2/3/4/5/9
132
Table 5-34 LPTIM
132
Table 5-35 CAN
132
Table 5-36 USART
132
Table 5-37 UART
132
Table 5-38 LPUART
133
Table 5-39 I2C
133
Table 5-40 SPI-I2S
133
Table 5-41 USB
133
Table 5-42 JTAG/SWD
133
Table 5-43 Other
133
GPIO Locking Mechanism
134
GPIO Register
134
GPIO Register Overview
134
Table 5-44 GPIO Register Overview
135
GPIO Mode Description Register (Gpiox_Pmode)
136
GPIO Type Definition (Gpiox_Potype)
136
GPIO Port Slew Rate Configuration Register (Gpiox_Sr)
137
GPIO Pull-Up/Pull-Down Description Register (Gpiox_Pupd)
137
GPIO Input Data Register (Gpiox_Pid)
138
GPIO Output Data Register (Gpiox_Pod)
138
GPIO Bit Set/Clear Register (Gpiox_Pbsc)
139
GPIO Configuration Lock Register (Gpiox_Plock)
139
GPIO Alternate Function Low Register (Gpiox_Afl)
140
GPIO Alternate Function High Register (Gpiox_Afh)
141
GPIO Bit Clear Register (Gpiox_Pbc)
142
GPIO Driver Strength Configuration Register (Gpiox_Ds)
142
AFIO Register
143
AFIO Register Overview
143
AFIO Mapping Configuration Control Register (AFIO_RMP_CFG)
143
Table 5-45 AFIO Register Overview
143
AFIO External Interrupt Configuration Register 1(AFIO_EXTI_CFG1)
144
AFIO External Interrupt Configuration Register 2(AFIO_EXTI_CFG2)
145
AFIO External Interrupt Configuration Register 3(AFIO_EXTI_CFG3)
146
AFIO External Interrupt Configuration Register 4(AFIO_EXTI_CFG4)
147
Interrupts and Events
148
Nested Vector Interrupt Register
148
Systick Calibration Value Register
148
Interrupt and Exception Vectors
148
Table 6-1 Vector Table
148
External Interrupt/Event Controller (EXTI)
151
Introduction
151
Main Features
151
Functional Description
152
Figure 6-1 External Interrupt/Event Controller Block Diagram
152
EXTI Line Maping
153
Figure 6-2 External Interrupt Generic I/O Mapping
153
EXTI Registers
154
EXTI Register Overview
155
EXTI Interrupt Mask Register (EXTI_IMASK)
155
Table 6-2 EXTI Register Overview
155
EXTI Event Mask Register (EXTI_EMASK)
156
EXTI Rising Edge Trigger Configuration Register (EXTI_RT_CFG)
156
EXTI Falling Edge Trigger Configuration Register (EXTI_FT_CFG)
157
EXTI Software Interrupt Event Register (EXTI_SWIE)
157
EXTI Pending Register (EXTI_PEND)
158
EXTI Timestamp Trigger Source Selection Register (EXTI_TS_SEL)
158
DMA Controller
160
Introduction
160
Main Features
160
Block Diagram
161
Function Description
161
DMA Operation
161
Figure 7-1 DMA Block Diagram
161
Channel Priority and Arbitration
162
DMA Channels and Number of Transfers
162
Programmable Data Bit Width, Alignment and Endians
162
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)
163
Peripheral/Memory Address Incrementation
164
Channel Configuration Procedure
164
Flow Control
165
Table 7-2 Flow Control Table
165
Circular Mode
166
Error Management
166
Interrupt
166
DMA Request Mapping
166
Table 7-3 DMA Interrupt Request
166
Table 7-4 DMA Request Mapping
167
DMA Registers
168
DMA Register Overview
168
Table 7-5 DMA Register Overview
168
DMA Interrupt Status Register (DMA_INTSTS)
170
DMA Interrupt Flag Clear Register (DMA_INTCLR)
171
DMA Channel X Configuration Register (Dma_Chcfgx)
171
DMA Channel X Transfer Number Register (Dma_Txnumx)
173
DMA Channel X Peripheral Address Register (Dma_Paddrx)
174
DMA Channel X Memory Address Register (Dma_Maddrx)
174
DMA Channel X Channel Request Select Register (Dma_Chselx)
175
CRC Calculation Unit
177
CRC Introduction
177
CRC Main Features
177
CRC32 Module
177
CRC16 Module
177
CRC Function Description
178
Crc32
178
Crc16
178
Figure 8-1 CRC Calculation Unit Block Diagram
178
CRC Registers
179
CRC Register Overview
179
CRC32 Data Register (CRC_CRC32DAT)
179
CRC32 Independent Data Register (CRC_CRC32IDAT)
179
Table 8-1 CRC Register Overview
179
CRC32 Control Register (CRC_CRC32CTRL)
180
CRC16 Control Register (CRC_CRC16CTRL)
180
CRC16 Input Data Register (CRC_CRC16DAT)
181
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)
181
LRC Result Register (CRC_LRC)
182
Cryptographic Algorithm Hardware Acceleration Engine (SAC)
183
Advanced-Control Timers (TIM1 and TIM8)
184
TIM1 and TIM8 Introduction
184
Main Features of TIM1 and TIM8
184
TIM1 and TIM8 Function Description
185
Time-Base Unit
185
Figure 10-1 Block Diagram of TIM1 and TIM8
185
Prescaler Description
186
Counter Mode
186
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
186
Up-Counting Mode
186
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
187
Down-Counting Mode
189
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
189
Center-Aligned Mode
189
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
190
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
191
Counter Underflow
191
Repetition Counter
191
Figure 10-8 Repeat Count Sequence Diagram in Down-Counting Mode
192
Figure 10-9 Repeat Count Sequence Diagram in Up-Counting Mode
193
Figure 10-10 Repeat Count Sequence Diagram in Center-Aligned Mode
193
Clock Selection
194
Figure 10-11 Control Circuit in Normal Mode, Internal Clock Divided by 1
194
Figure 10-12 TI2 External Clock Connection Example
195
Figure 10-13 Control Circuit in External Clock Mode 1
196
Figure 10-14 External Trigger Input Block Diagram
196
Capture/Compare Channels
197
Figure 10-15 Control Circuit in External Clock Mode 2
197
Figure 10-16 Capture/Compare Channel (Example: Channel 1 Input Stage)
198
Figure 10-17 Capture/Compare Channel 1 Main Circuit
199
Input Capture Mode
200
Figure 10-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)
200
Figure 10-19 Output Part of Channelx (X= 4)
200
PWM Input Mode
201
Forced Output Mode
202
Figure 10-20 PWM Input Mode Timing
202
Output Compare Mode
203
PWM Mode
204
PWM Center-Aligned Mode
204
Figure 10-21 Output Compare Mode, Toggle on OC1
204
Figure 10-22 Center-Aligned PWM Waveform (AR=8)
205
Figure 10-23 Edge-Aligned PWM Waveform (APR=8)
206
One-Pulse Mode
207
Clearing the Ocxref Signal on an External Event
208
Complementary Outputs with Dead-Time Insertion
209
Figure 10-24 Clearing the Ocxref of Timx
209
Figure 10-25 Complementary Output with Dead-Time Insertion
210
Break Function
211
Figure 10-26 Output Behavior in Response to a Break
213
Debug Mode
213
Timx and External Trigger Synchronization
213
Slave Mode: Reset Mode
213
Slave Mode: Trigger Mode
214
Figure 10-27 Control Circuit in Reset Mode
214
Slave Mode: Gated Mode
215
Figure 10-28 Control Circuit in Trigger Mode
215
Figure 10-29 Control Circuit in Gated Mode
216
Timer Synchronization
217
6-Step PWM Generation
217
Figure 10-30 Control Circuit in Trigger Mode + External Clock Mode2
217
Encoder Interface Mode
218
Figure 10-31 6-Step PWM Generation, COM Example (OSSR=1)
218
Table 10-1 Counting Direction Versus Encoder Signals
219
Figure 10-32 Example of Counter Operation in Encoder Interface Mode
219
Interfacing with Hall Sensor
220
Figure 10-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
220
Advanced-Control
221
Figure 10-34 Example of Hall Sensor Interface
221
Timx Registers(X=1, 8)
222
Timx Register Overview
222
Table 10-2 Timx Register Overview
222
Control Register 1 (Timx_Ctrl1)
223
Control Register 2 (Timx_Ctrl2)
225
Slave Mode Control Register (Timx_Smctrl)
227
Dma/Interrupt Enable Registers (Timx_Dinten)
229
Table 10-3 Timx Internal Trigger Connection
229
Status Registers (Timx_Sts)
231
Event Generation Registers (Timx_Evtgen)
233
Capture/Compare Mode Register 1 (Timx_Ccmod1)
234
Capture/Compare Mode Register 2 (Timx_Ccmod2)
237
Capture/Compare Enable Registers (Timx_Ccen)
239
Table 10-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function
241
Counters (Timx_Cnt)
242
Prescaler (Timx_Psc)
242
Auto-Reload Register (Timx_Ar)
242
Repeat Count Registers (Timx_Repcnt)
242
Capture/Compare Register 1 (Timx_Ccdat1)
243
Capture/Compare Register 2 (Timx_Ccdat2)
243
Capture/Compare Register 3 (Timx_Ccdat3)
244
Capture/Compare Register 4 (Timx_Ccdat4)
244
Break and Dead-Time Registers (Timx_Bkdt)
245
DMA Control Register (Timx_Dctrl)
247
DMA Transfer Buffer Register (Timx_Daddr)
247
Capture/Compare Mode Registers 3(Timx_Ccmod3)
248
Capture/Compare Register 5 (Timx_Ccdat5)
249
Capture/Compare Register 6 (Timx_Ccdat6)
249
General-Purpose Timers (TIM2, TIM3, TIM4, TIM5 and TIM9)
250
General-Purpose Timers Introduction
250
Main Features of General-Purpose Timers
250
General-Purpose Timers Description
251
Time-Base Unit
251
Figure 11-1 Block Diagram of Timx（X=2, 3 ,4 ,5 and 9
251
Counter Mode
252
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
252
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
254
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
255
Figure 11-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N
256
Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N
257
Clock Selection
258
Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)
258
Figure 11-8 Control Circuit in Normal Mode, Internal Clock Divided by 1
259
Figure 11-9 TI2 External Clock Connection Example
260
Figure 11-10 Control Circuit in External Clock Mode 1
261
Figure 11-11 External Trigger Input Block Diagram
261
Capture/Compare Channels
262
Figure 11-12 Control Circuit in External Clock Mode 2
262
Figure 11-13 Capture/Compare Channel (Example: Channel 1 Input Stage)
263
Figure 11-14 Capture/Compare Channel 1 Main Circuit
264
Input Capture Mode
265
Figure 11-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example
265
PWM Input Mode
266
Forced Output Mode
267
Output Compare Mode
267
Figure 11-16 PWM Input Mode Timing
267
PWM Mode
269
Figure 11-17 Output Compare Mode, Toggle on OC1
269
Figure 11-18 Center-Aligned PWM Waveform (AR=8)
270
Figure 11-19 Edge-Aligned PWM Waveform (APR=8)
271
One-Pulse Mode
272
Figure 11-20 Example of One-Pulse Mode
272
Clearing the Ocxref Signal on an External Event
273
Debug Mode
274
Timx and External Trigger Synchronization
274
Timer Synchronization
274
Figure 11-21 Control Circuit in Reset Mode
274
Figure 11-22 Block Diagram of Timer Interconnection
275
Figure 11-23 TIM2 Gated by OC1REF of TIM1
276
Figure 11-24 TIM2 Gated by Enable Signal of TIM1
277
Figure 11-25 Trigger TIM2 with an Update of TIM1
278
Encoder Interface Mode
279
Figure 11-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1
279
Table 11-1 Counting Direction Versus Encoder Signals
280
Figure 11-27 Example of Counter Operation in Encoder Interface Mode
280
Interfacing with Hall Sensor
281
Timx Registers(X=2, 3 ,4 ,5 and 9)
281
Timx Register Overview
281
Figure 11-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted
281
Control Register 1 (Timx_Ctrl1)
283
Control Register 2 (Timx_Ctrl2)
285
Slave Mode Control Register (Timx_Smctrl)
286
Dma/Interrupt Enable Registers (Timx_Dinten)
288
Table 11-3 Timx Internal Trigger Connection
288
Status Registers (Timx_Sts)
289
Event Generation Registers (Timx_Evtgen)
291
Capture/Compare Mode Register 1 (Timx_Ccmod1)
292
Capture/Compare Mode Register 2 (Timx_Ccmod2)
295
Capture/Compare Enable Registers (Timx_Ccen)
297
Counters (Timx_Cnt)
298
Prescaler (Timx_Psc)
298
Auto-Reload Register (Timx_Ar)
298
Table 11-4 Output Control Bits of Standard Ocx Channel
298
Capture/Compare Register 1 (Timx_Ccdat1)
299
Capture/Compare Register 2 (Timx_Ccdat2)
299
Capture/Compare Register 3 (Timx_Ccdat3)
300
Capture/Compare Register 4 (Timx_Ccdat4)
300
DMA Control Register (Timx_Dctrl)
301
DMA Transfer Buffer Register (Timx_Daddr)
302
Basic Timers (TIM6 and TIM7)
303
Basic Timers Introduction
303
Main Features of Basic Timers
303
Figure 12-1 Block Diagram of Timx（X = 6 and 7
303
Basic Timers Description
304
Time-Base Unit
304
Figure 12-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4
304
Counter Mode
305
Figure 12-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N
306
Figure 12-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1
307
Clock Selection
308
Debug Mode
308
Timx Registers(X = 6 and 7)
308
Figure 12-5 Control Circuit in Normal Mode, Internal Clock Divided by 1
308
Timx Register Overview
309
Control Register 1 (Timx_Ctrl1)
309
Table 12-1 Timx Register Overview
309
Control Register 2 (Timx_Ctrl2)
311
Dma/Interrupt Enable Registers (Timx_Dinten)
311
Status Registers (Timx_Sts)
312
Event Generation Registers (Timx_Evtgen)
312
Counters (Timx_Cnt)
313
Prescaler (Timx_Psc)
313
Automatic Reload Register (Timx_Ar)
314
Low Power Timer (LPTIM)
315
Introduction
315
Main Features
315
Block Diagram
316
Function Description
316
LPTIM Clocks and On-Off Control
316
Figure 13-1 LPTIM Diagram
316
Prescaler
317
Glitch Filter
317
Table 13-1 Pre-Scaler Division Ratios
317
Timer Enable
318
Trigger Multiplexer
318
Table 13-2 9 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits
318
Figure 13-2 Glitch Filter Timing Diagram
318
Operating Mode
319
Figure 13-3 LPTIM Output Waveform, Continuous Counting Mode Configuration
319
Figure 13-4 PTIM Output Waveform, Single Counting Mode Configuration
320
Waveform Generation
321
Figure 13-5 LPTIM Output Waveform, Single Counting Mode Configuration and One-Time Mode Activated
321
Register Update
322
Figure 13-6 Waveform Generation
322
Counter Mode
323
Encoder Mode
324
Table 13-3 Encoder Counting Scenarios
324
Non-Orthogonal Encoder Mode
325
Figure 13-7 Encoder Mode Counting Sequence
325
Timeout Function
326
Figure 13-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally
326
Figure 13-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working
326
LPTIM Interrupts
327
LPTIM Registers
327
LPTIM Register Overview
327
Table 13-4 Interruption Events
327
LPTIM Interrupt and Status Register (LPTIM_INTSTS)
328
LPTIM Interrupt Clear Register (LPTIM_INTCLR)
329
LPTIM Interrupt Enable Register (LPTIM_INTEN)
330
LPTIM Configuration Register (LPTIM_CFG)
331
LPTIM Control Register (LPTIM_CTRL)
334
LPTIM Compare Register (LPTIM_COMP)
335
LPTIM Auto-Reload Register (LPTIM_ARR)
335
LPTIM Counter Register (LPTIM_CNT)
335
Real Time Clock (RTC)
337
Introduction
337
Main Feature
337
Function Description
340
RTC Block Diagram
340
Figure 14-1 RTC Block Diagram
340
GPIO Controlled by RTC
341
RTC Register Write Protection
341
RTC Clock and Prescaler
341
RTC Calendar
342
Calendar Initialization and Configuration
342
Calendar Reading
343
Calibration Clock Output
344
Programmable Alarm
344
Alarm Configuration
344
Alarm Output
344
Periodic Automatic Wakeup
345
Wakeup Timer Configuration
345
Timestamp Function
345
Tamper Detection
346
Daylight Saving Time Configuration
347
RTC Reset
347
RTC Sub-Second Register Shift Operation
347
RTC Digital Clock Precision Calibration
347
RTC Low Power Mode
349
RTC Registers
349
RTC Register Overview
349
Table 14-1 RTC Register Overview
349
RTC Calendar Time Register (RTC_TSH)
350
RTC Calendar Date Register (RTC_DATE)
351
RTC Control Register (RTC_CTRL)
352
RTC Initial Status Register (RTC_INITSTS)
354
RTC Prescaler Register (RTC_PRE)
356
RTC Wakeup Timer Register (RTC_WKUPT)
357
RTC Alarm a Register (RTC_ALARMA)
357
RTC Alarm B Register (RTC_ALARMB)
358
RTC Write Protection Register (RTC_WRP)
359
RTC Sub-Second Register (RTC_SUBS)
360
RTC Shift Control Register (RTC_SCTRL)
360
RTC Timestamp Time Register (RTC_TST)
361
RTC Timestamp Date Register (RTC_TSD)
361
RTC Timestamp Sub-Second Register (RTC_TSSS)
362
RTC Calibration Register (RTC_CALIB)
363
RTC Tamper Configuration Register (RTC_TMPCFG)
363
RTC Alarm a Sub-Second Register (RTC_ALRMASS)
366
RTC Alarm B Sub-Second Register (RTC_ALRMBSS)
367
RTC Option Register (RTC_OPT)
368
RTC Backup Registers (RTC_BKP(1~20))
368
Independent Watchdog (IWDG)
369
Introduction
369
Main Features
369
Function Description
370
Register Access Protection
370
Figure 15-1 Functional Block Diagram of the Independent Watchdog Module
370
Debugging Mode
371
User Interface
371
Operate Flow
371
Table 15-1 IWDG Counting Maximum and Minimum Reset Time
371
IWDG Configuration Flow
372
IWDG Registers
372
IWDG Register Overview
372
Table 15-2 IWDG Register Overview
372
IWDG Key Register (IWDG_KEY)
373
IWDG Pre-Scaler Register (IWDG_PREDIV)
373
IWDG Reload Register (IWDG_RELV)
374
IWDG Status Register (IWDG_STS)
374
Window Watchdog (WWDG)
376
Introduction
376
Main Features
376
Function Description
376
Figure 16-1 Watchdog Block Diagram
376
Timing for Refresh Watchdog and Interrupt Generation
377
Figure 16-2 Refresh Window and Interrupt Timing of WWDG
377
Debug Mode
378
User Interface
378
WWDG Configuration Flow
378
Table 16-1 Maximum and Minimum Counting Time of WWDG
378
WWDG Registers
379
WWDG Register Overview
379
WWDG Control Register (WWDG_CTRL)
379
WWDG Config Register (WWDG_CFG)
379
Table 16-2 WWDG Register Overview
379
WWDG Status Register (WWDG_STS)
380
Analog to Digital Conversion (ADC)
381
Introduction
381
Main Features
381
Function Description
382
ADC Clock
383
Table 17-1 ADC Pins
383
Figure 17-1 Block Diagram of a Single ADC
383
ADC Switch Control
384
Figure 17-2 ADC Clock
384
Channel Selection
385
Figure 17-3 ADC Channels and Pin Connections
386
Internal Channel
387
Single Conversion Mode
387
Continuous Conversion Mode
387
Timing Diagram
387
Analog Watchdog
388
Table 17-2 Analog Watchdog Channel Selection
388
Figure 17-4 Timing Diagram
388
Scanning Mode
389
Injection Channel Management
389
Discontinuous Mode
390
Figure 17-5 Injection Conversion Delay
390
Calibration
391
Data Aligned
391
Figure 17-6 Calibration Sequence Diagram
391
Programmable Channel Sampling Time
392
Externally Triggered Conversion
392
Table 17-3 Right-Align Data
392
Table 17-4 Left-Aligne Data
392
DMA Requests
393
Table 17-5 ADC Is Used for External Triggering of Regular Channels
393
Table 17-6 ADC Is Used for External Triggering of Injection Channels
393
Temperature Sensor
394
Temperature Sensor Using Flow
394
Figure 17-7 Temperature Sensor and VREFINT Diagram of the Channel
394
ADC Interrupt
395
ADC Registers
395
ADC Register Overview
395
Table 17-7 ADC Interrupt
395
Table 17-8 ADC Register Overview
395
ADC Status Register (ADC_STS)
396
ADC Control Register 1 (ADC_CTRL1)
398
ADC Control Register 2 (ADC_CTRL2)
400
ADC Sampling Time Register 1 (ADC_SAMPT1)
402
ADC Sampling Time Register 2 (ADC_SAMPT2)
402
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1
403
ADC Watchdog High Threshold Register (ADC_WDGHIGH)
403
ADC Watchdog Low Threshold Register (ADC_WDGLOW)
404
ADC Regular Sequence Register 1 (ADC_RSEQ1)
404
ADC Regular Sequence Register 2 (ADC_RSEQ2)
405
ADC Regular Sequence Register 3 (ADC_RSEQ3)
405
ADC Injection Sequence Register (ADC_JSEQ)
406
ADC Injection Data Register X (Adc_Jdatx) (X= 1
406
ADC Regulars Data Register (ADC_DAT)
407
ADC Differential Mode Selection Register (ADC_DIFSEL)
407
ADC Calibration Factor (ADC_CALFACT)
408
ADC Control Register 3 (ADC_CTRL3)
408
ADC Sampling Time Register 3 (ADC_SAMPT3)
410
Digital to Analog Conversion (DAC)
411
Introduction
411
Main Features
411
DMA Support
411
Table 18-1 DAC Pins
412
Figure 18-1 Block Diagram of a DAC Channel
412
DAC Function Description and Operation Description
413
DAC Enable
413
DAC Output Buffer
413
DAC Data Format
413
DAC Trigger
414
Table 18-2 DAC External Trigger
414
Figure 18-2 Data Register of Single DAC Channel Mode
414
DAC Conversion
415
DAC Output Voltage
415
DMA Requests
415
Figure 18-3 Time Diagram of Transitions with Trigger Disable
415
The Noise
416
Figure 18-4 LFSR Algorithm for DAC
416
Triangular Wave Generation
417
Figure 18-5 DAC Conversion with LFSR Waveform Generation (Enable Software Trigger)
417
DAC Register
418
DAC Registers Overview
418
Table 18-3 DAC Registers Overvie
418
Figure 18-6 Triangle Wave Generation of DAC
418
Figure 18-7 DAC Conversion with Trigonometry Generation (Enable Software Trigger)
418
DAC Control Register (DAC_CTRL)
419
DAC Software Trigger Register (DAC_SOTTR)
420
Bit Right Aligned Data Hold Register for DAC (DAC_DR12CH)
421
Bit Left Aligned Data Hold Register for DAC (DAC_DL12CH)
421
8-Bit Right-Aligned Data Hold Register for DAC (DAC_DR8CH)
421
DAC Data Output Register (DAC_DATO)
422
Comparator (COMP)
423
COMP System Connection Block Diagram
423
Figure 19-1 Comparator Controller Functional Diagram
423
COMP Features
424
COMP Configuration Process
424
COMP Working Mode
425
Window Mode
425
Independent Comparator
425
Comparator Interconnection
425
Interrupt
426
COMP Register
427
COMP Register Overview
427
Table 19-1 COMP Register Overview
427
COMP Interrupt Enable Register (COMP_INTEN)
428
COMP Low Power Select Register (COMP_LPCKSEL)
428
COMP Window Mode Register (COMP_WINMODE)
429
COMP Lock Register (COMP_LOCK)
429
COMP1 Control Register (COMP1_CTRL)
430
COMP1 Filter Register (COMP1_FILC)
432
COMP1 Filter Frequency Division Register (COMP1_FILP)
432
COMP2 Control Register (COMP2_CTRL)
433
COMP2 Filter Register (COMP2_FILC)
434
COMP2 Filter Frequency Division Register (COMP2_FILP)
435
COMP2 Output Select Register (COMP2_OSEL)
435
COMP Reference Voltage Register (COMP_VREFSCL)
436
COMP Test Register(COMP_TEST)
436
COMP Interrupt Status Register (COMP_INTSTS)
437
Operational Amplifier (OPAMP)
438
Main Features
438
OPAMP Function Description
438
OPAMP Working Mode
439
OPAMP Independent Op Amp Mode
439
Figure 20-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram
439
OPAMP Follow Mode
440
Figure 20-2 OPAMP Independent Op Amp Mode
440
OPAMP Internal Gain (PGA) Mode
441
Figure 20-3 Follow Mode
441
OPAMP with Filtered Internal Gain Mode
442
Figure 20-4 Internal Gain Mode
442
Figure 20-5 Internal Gain Mode with Filtering
442
OPAMP Calibration
443
OPAMP Independent Write Protection
443
OPAMP TIMER Controls the Switching Mode
443
OPAMP Register
443
OPAMP Register Overview
443
Table 20-1 OPAMP Register Overview
443
OPAMP Control Status Register (OPAMP1_CS)
444
OPAMP Control Status Register (OPAMP2_CS)
445
OPAMP Lock Register (OPAMP_LOCK)
447
Low Power Rotation Counter (LPRCNT)
448
Introduction
448
Main Features
448
Functional Description
449
LPRCNT Diagram
449
Introduction to the Principle of Damped Oscillation
449
Figure 21-1 LPRCNT Block Diagram
449
State Machine Judgment and Rotation Position
450
Calibration Mode and Normal Mode
451
Table 21-1 Sensor Damped Oscillation State Machine Comparison Table
451
Figure 21-2 Rotating Object Damping Oscillation Detection Principle
451
LPRCNT Comparator Filtering
452
LPRCNT Operation Instructions
452
Channel Configuration
452
Figure 21-3 LPRCNT Module Comparator Filtering Block Diagram
452
LPRCNT Module Operation in Calibration Mode
454
Figure 21-4 LC Damped Oscillation Process
454
Figure 21-5 Three-Way LC Working Timing Diagram
454
LPRCNT Normal Working Mode Operation
455
LPRCNT Registers
455
LPRCNT Register Overview
455
LPRCNT Control Register (LPRCNT_CTRL)
456
Table 21-2 LPRCNT Register Overview
456
LPRCNT Interrupt Status Register
458
LPRCNT Scan Control Register(LPRCNT_SCTRL)
458
LPRCNT Sensor Channel 0 Threshold Register(LPRCNT_CH0CFG0)
459
LPRCNT Sensor Channel 0 Time Control Register (LPRCNT_CH0CFG1)
459
LPRCNT Sensor Channel 1 Threshold Register (LPRCNT_CH1CFG0)
460
LPRCNT Sensor Channel 1 Time Control Register (LPRCNT_CH1CFG1)
460
LPRCNT Sensor Channel 2 Threshold Register (LPRCNT_CH2CFG0)
460
LPRCNT Sensor Channel 2 Time Control Register (LPRCNT_CH2CFG1)
461
LPRCNT Command Register (LPRCNT_CMD)
461
LPRCNT Calibration Register 0 (LPRCNT_CAL0)
462
LPRCNT Calibration Register 1(LPRCNT_CAL1)
462
LPRCNT Calibration Register 2(LPRCNT_CAL2)
463
LPRCNT Calibration Register 3 (LPRCNT_CAL3)
463
Liquid Crystal Display Controller (LCD)
466
Introduction
466
Main Features
466
Functional Block Diagram
467
Figure 22-1 LCD Controller Block Diagram
467
Functional Description
468
Frequency Generator
468
Table 22-1 Frame Rate Calculation Example
468
Common End Driver
469
COM Signal Bias
469
Figure 22-2 Odd-Even Frames Example(1/4 Duty Cycle, 1/3 Bias)
470
Segment Driver
471
Figure 22-3 Static Duty Cycle Example
471
Figure 22-4 1/2 Duty Cycle, 1/2 Bias
472
Figure 22-5 1/3 Duty Cycle, 1/3 Bias
473
Figure 22-6 1/4 Duty Cycle, 1/3 Bias
474
Blink Function
475
Figure 22-7 1/8 Duty Cycle, 1/4 Bias
475
Voltage Generator and Contrast Control
476
Table 22-2 Blink Frequency Configure Example
476
Figure 22-8 LCD Drive Voltage Control
477
Double Buffer Display
478
COM and SEG Multiplexing
478
Figure 22-9 Dead Time
478
Table 22-3 COM and SEG Pins Mapping Table
479
Working Process
483
Low Power Mode
483
Interrupt Request
483
LCD Controller Registers
483
LCD Controller Register Overview
484
Table 22-4 LCD Controller Register Overview
484
LCD Control Register (LCD_CTRL)
485
LCD Frame Control Register (LCD_FCTRL)
486
LCD Status Register (LCD_STS)
488
LCD Clear Register (LCD_CLR)
489
LCD Display Memory Register (Lcd_Ram1_Comx X = 0
490
LCD Display Memory Register (Lcd_Ram2_Comx X = 0
490
LCD Display Memory Register (Lcd_Ram2_Comx X = 4
491
I2C Interface
492
Introduction
492
Main Features
492
Function Description
492
SDA and SCL Line Control
493
Software Communication Process
493
Start and Stop Conditions
494
Figure 23-1 I 2 C Functional Block Diagram
494
Figure 23-2 I2C Bus Protocol
494
Clock Synchronization and Arbitration
494
Clock Synchronization
495
Figure 23-3 Slave Transmitter Transfer Sequence Diagram
497
Figure 23-4 Slave Receiver Transfer Sequence Diagram
498
Figure 23-5 Master Transmitter Transfer Sequence Diagram
500
Figure 23-6 Master Receiver Transfer Sequence Diagram
502
Error Conditions Description
503
DMA Application
504
Transmit Process
504
Receive Process
504
Packet Error Check
505
Smbus
506
Device Identification
506
Table 23-1 Comparison between Smbus and I2C
506
Bus Protocol
507
Address Resolution Protocol
507
Debug Mode
508
Interrupt Request
508
Table 23-2 I 2 C Interrupt Request
508
I2C Registers
509
I2C Register Overview
509
Table 23-3 I2C Register Overview
509
I2C Control Register 1 (I2C_CTRL1)
510
I2C Control Register 2 (I2C_CTRL2)
512
I2C Own Address Register 1 (I2C_OADDR1)
513
I2C Own Address Register 2 (I2C_OADDR2)
514
I2C Data Register (I2C_DAT)
514
I2C Status Register 1 (I2C_STS1)
515
I2C Status Register 2 (I2C_STS2)
518
I2C Clock Control Register (I2C_CLKCTRL)
519
I2C Rise Time Register (I2C_TMRISE)
520
Universal Synchronous Asynchronous Receiver Transmitter (USART)
522
Introduction
522
Main Features
522
Functional Block Diagram
523
Function Description
523
Figure 24-1 USART Block Diagram
523
USART Frame Format
524
Figure 24-2 Word Length = 8 Setting
524
Transmitter
525
Table 24-1 Stop Bit Configuration
525
Figure 24-3 Word Length = 9 Setting
525
Figure 24-4 Configuration Stop Bit
526
Single Byte Communication
527
Receiver
527
Start Bit Detection
527
Figure 24-5 TXC/TXDE Changes During Transmission
527
Figure 24-6 Start Bit Detection
528
Framing Error
529
Overrun Error
530
Table 24-2 Data Sampling for Noise Detection
530
Generation of Fractional Baud Rate
530
Table 24-3 Error Calculation When Setting Baud Rate
531
Receiver's Tolerance Clock Deviation
532
Parity Control
532
Table 24-4 When Div_Decimal = 0. Tolerance of USART Receiver
532
Table 24-5 When Div_Decimal != 0. Tolerance of USART Receiver
532
Table 24-6 Frame Format
532
Even Parity
533
Odd Parity
533
DMA Application
533
Figure 24-7 Transmission Using DMA
534
Hardware Flow Control
535
Figure 24-8 Reception Using DMA
535
Figure 24-9 Hardware Flow Control between Two USART
535
Figure 24-10 RTS Flow Control
536
Figure 24-11 CTS Flow Controls
537
Multiprocessor Communication
537
Idle Line Detection
537
Figure 24-12 Mute Mode Using Idle Line Detection
538
Synchronous Mode
539
Figure 24-13 Mute Mode Detected Using Address Mark
539
Figure 24-14 USART Synchronous Transmission Example
540
Figure 24-15 USART Data Clock Timing Example (WL=0)
540
Single-Wire Half-Duplex Mode
541
Figure 24-16 USART Data Clock Timing Example (WL=1)
541
Figure 24-17 RX Data Sampling / Holding Time
541
Irda SIR ENDEC Mode
542
LIN Mode
543
Figure 24-18 Irdasirendec-Block Diagram
543
Figure 24-19 Irda Data Modulation (3/16)-Normal Mode
543
Figure 24-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)
545
Smartcard Mode (ISO7816)
546
Figure 24-21 Break Detection and Framing Error Detection in LIN Mode
546
Figure 24-22 ISO7816-3 Asynchronous Protocol
547
Interrupt Request
548
Table 24-7 USART Interrupt Request
548
Figure 24-23 Use 1.5 Stop Bits to Detect Parity Errors
548
Mode Support
549
USART Registers
549
USART Register Overview
549
Table 24-8 USART Mode Setting
549
Table 24-9 USART Register Overview
549
USART Status Register (USART_STS)
550
USART Data Register (USART_DAT)
552
USART Baud Rate Register (USART_BRCF)
553
USART Control Register 1 Register (USART_CTRL1)
553
USART Control Register 2 Register (USART_CTRL2)
555
USART Control Register 3 Register (USART_CTRL3)
556
USART Guard Time and Prescaler Register (USART_GTP)
558
Low Power Universal Asynchronous Receiver Transmitter (LPUART)
560
Introduction
560
Main Features
560
Functional Block Diagram
561
Function Description
561
Figure 25-1 LPUART Block Diagram
561
LPUART Frame Format
562
Transmitter
562
Figure 25-2 Frame Format
562
Receiver
564
Figure 25-3 TXC Changes During Transmission
564
Fractional Baud Rate Generation
566
Table 25-1 Data Sampling for Noise Detection
566
Figure 25-4 Data Sampling for Noise Detection
566
Parity Control
568
DMA Application
568
Table 25-2 Parity Frame Format
568
Figure 25-5 Sending Using DMA
569
Hardware Flow Control
570
Figure 25-6 Receiving with DMA
570
Figure 25-7 Hardware Flow Control between Two LPUART
570
Figure 25-8 RTS Flow Control
571
Figure 25-9 CTS Flow Control
571
Low Power Wake up
572
Interrupt Request
572
LPUART Registers
572
LPUART Register Overview
572
Table 25-3 LPUART Interrupt Requests
572
Table 25-4 LPUART Register Overview
572
LPUART Status Register (LPUART_STS)
573
LPUART Interrupt Enable Register (LPUART_INTEN)
574
LPUART Control Register (LPUART_CTRL)
575
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)
576
LPUART Data Register (LPUART_DAT)
577
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)
577
LPUART Wake up Data Register (LPUART_WUDAT)
577
Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)
579
Introduction
579
Main Features
579
SPI Features
579
I2S Features
579
SPI Function Description
580
General Description
580
Figure 26-1 SPI Block Diagram
580
Figure 26-2 Selective Management of Hardware/Software
581
Figure 26-3 Master and Slave Applications
582
Data Format
583
SPI Work Mode
583
Figure 26-4 Data Clock Timing Diagram
583
Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode
584
Figure 26-6 Schematic Diagram of TE/BUSY Change When Host Transmits Continuously in One-Way Only Mode
585
Figure 26-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode (BIDIRMODE = 0 and RONLY = 1)
586
Figure 26-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in Full
586
Duplex Mode
586
Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode
587
Status Flag
589
Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted Discontinuously
589
Disabling the SPI
590
SPI Communication Using DMA
591
CRC Calculation
592
Figure 26-11 Transmission Using DMA
592
Figure 26-12 Reception Using DMA
592
Error Flag
593
SPI Interrupt
594
Table 26-1 SPI Interrupt Request
594
I2S Function Description
595
Figure 26-13 I 2 S Block Diagram
595
Supported Audio Protocols
596
Figure 26-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)
597
Figure 26-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)
597
Figure 26-16 I 2 S Philips Protocol Standard Waveform (16-Bit Extended to 32-Bit Packet Frame, CLKPOL = 0)
598
Figure 26-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0
599
Figure 26-18 MSB Aligns 24-Bit Data, CLKPOL = 0
599
Figure 26-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
600
Figure 26-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0
600
Figure 26-21 LSB Aligns 24-Bit Data, CLKPOL = 0
601
Figure 26-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0
601
Figure 26-23 PCM Standard Waveform (16 Bits)
602
Figure 26-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)
602
Clock Generator
603
Figure 26-25 I 2 S Clock Generator Structure
603
Figure 26-26 Audio Sampling Frequency Definition
603
I2S Transmission and Reception Sequence
604
Table 26-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency
604
Status Flag
606
Error Flag
607
I2S Interrupt
607
DMA Function
608
SPI and I2S Registers
608
SPI Register Overview
608
Table 26-3 I 2 S Interrupt Request
608
Table 26-4 SPI Register Overview
608
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)
609
SPI Control Register 2 (SPI_CTRL2)
611
SPI Status Register (SPI_STS)
612
SPI Data Register (SPI_DAT)
613
SPI CRC Polynomial Register (SPI_CRCPOLY) (Not Used in I2S Mode)
613
SPI RX CRC Register (SPI_CRCRDAT) (Not Used in I2S Mode)
614
SPI TX CRC Register（Spi_ CRCTDAT
614
SPI_I2S Configuration Register（Spi_I2Scfg
615
SPI_I2S Prescaler Register (SPI_I2SPREDIV)
616
Controller Area Network (CAN)
618
Introduction to CAN
618
Main Features of CAN
618
CAN Overall Introduction
618
CAN Module
619
CAN Working Mode
619
Figure 27-1 Topology of CAN Network
619
Normal Mode
620
Initialization Mode
620
Sleep Mode (Low Power)
620
Send Mailbox
621
Receiving Filter
621
Receive FIFO
621
Figure 27-2 CAN Working Mode
621
CAN Test Mode
622
Loopback Mode
622
Figure 27-3 Single CAN Block Diagram
622
Figure 27-4 Loopback Mode
623
Figure 27-5 Silent Mode
624
Figure 27-6 Loopback Silent Mode
624
CAN Debugging Mode
625
CAN Function Description
625
Send Processing
625
Send Priority
625
Cancel Sending
626
Time Triggered Communication Mode
626
Non-Automatic Retransmission Mode
626
Receiving Management
627
Figure 27-7 Send Mailbox Status
627
Figure 27-8 Receive FIFO Status
628
Identifier Filtering
629
Mask Mode
630
Figure 27-9 Filter Bit Width Setting-Register Organization
630
Table 27-1 Examples of Filter Numbers
631
Message Storage
632
Figure 27-10 Examples of Filter Mechanisms
632
Bit Time Characteristic
633
Table 27-2 Send Mailbox Register List
633
Table 27-3 Receive Mailbox Register List
633
Figure 27-11 Bit Sequence
634
Figure 27-12 Various CAN Frames
635
CAN Interrupt
636
Figure 27-13 Event Flag and Interrupt Generation
636
Error Management
637
Bus-Off Recovery
637
Figure 27-14 CAN Error State Diagram
637
CAN Configuration Flow
638
CAN Registers
639
Register Description
639
CAN Register Overview
640
Table 27-4 CAN Register Overview
640
CAN Control and Status Register
643
CAN Mailbox Register
654
CAN Filter Register
659
Universal Serial Bus Full-Speed Device Interface (Usb_Fs_Device)
663
Introduction
663
Main Features
663
Clock Configuration
664
Functional Description
664
Figure 28-1 USB Device Block Diagram
664
Access Packet Buffer Memory
665
Buffer Description Table
666
Figure 28-2 the User Applications on the Microcontrollers and the USB Modules Access Packet Buffer Memory
666
Double-Buffered Endpoints
667
Figure 28-3 the Relationship between the Buffer Description Table and the Endpoint Packet Buffer
667
Table 28-1 DATTOG and SW_BUF Definitions
668
Table 28-2 How to Use Double Buffering
668
Figure 28-4 Double Buffered Bulk Endpoint Example
669
USB Transfer
670
Control Transfer
671
Figure 28-5 Control Transfer
673
USB Events and Interrupts
674
Table 28-3 How to Use Isochronous Double Buffering
674
Table 28-4 Resume Event Detection
675
USB Interrupt
676
Endpoint Initialization
676
USB Registers
676
USB Register Overview
677
Table 28-5 USB Register Overview
677
USB Endpoint N Register (Usb_Epn), N=[0
678
Table 28-6 Receive Status Code
680
Table 28-7 Send Status Code
680
USB Control Register (USB_CTRL)
681
USB Interrupt Status Register (USB_STS)
682
USB Frame Number Register (USB_FN)
685
USB Device Address Register (USB_ADDR)
685
USB Packet Buffer Description Table Address Register (USB_BUFTAB)
686
Buffer Description Table
686
Send Buffer Address Register N (Usb_Addrn_Tx)
687
Send Data Byte Number Register N (Usb_Cntn_Tx)
687
Receive Buffer Address Register N (Usb_Addrn_Rx)
687
Receive Data Byte Number Register N (Usb_Cntn_Rx)
688
Table 28-8 Endpoint Packet Receive Buffer Size Definition
688
Debug Support (DBG)
690
Overview
690
Figure 29-1 N32L43X Level and Cortex
690
TM -M4F Level Debugging Block Diagram
690
JTAG/SWD Function
691
Switch JTAG/SWD Interface
691
Pin Allocation
691
MCU Debug Function
692
Low-Power Mode Debug Support
692
Table 29-1 Debug Port Pin
692
Peripherals Debug Support
693
DBG Registers
693
DBG Register Overview
693
ID Register (DBG_ID)
693
Table 29-2 DBG Register Overview
693
Debug Control Register (DBG_CTRL)
694
Unique Device Serial Number (UID)
696
Introduction
696
UID Register
696
UCID Register
696
31 Version History
697
32 Notice
698

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