Altera MegaCore Manuals

Manuals and User Guides for Altera MegaCore. We have 1 Altera MegaCore manual available for free PDF download: User Manual

Altera MegaCore User Manual

Altera MegaCore User Manual (180 pages)

Brand: Altera | Category: Network Router | Size: 1.33 MB

Table of Contents

Table of Contents
3
About this User Guide

9
- Introduction
  9
- References
  9
- Revision History
  10
- How to Contact Altera
  10
- Typographic Conventions
  11
Chapter 1. About this Megacore Function

13
- Release Information
  13
- Device Family Support
  13
- Features
  14
- General Description
  16
- Megacore Verification
  20
  - Hardware Verification
    20
    
    Optical Platform
    20
    
    Copper Platform
    21
- Performance
  21
- Installation and Licensing
  22
  - Opencore Plus Evaluation
    23
  - Opencore Plus Time-Out Behavior
    23
Chapter 2. Getting Started

25
Chapter 3. Configuring the Megacore Function

35
- Introduction
  35
- Core Configuration
  36
  - Core Variation
    36
  - Interface
    37
  - Use Transceiver Block
    37
- MAC Options
  38
  - Ethernet MAC Options
    38
  - MDIO Module
    39
- FIFO Options
  40
  - Width and Memory Type
    40
  - Depth
    41
- PCS/SGMII Options
  41
  - Pcs/Sgmii
    41
Chapter 4. Specifications

43
- 10/100/1000 Ethernet MAC
  43
  - Ethernet Frame Format
    44
  - MAC Receive Operation
    47
    
    Preamble Processing
    47
    
    Collision Detection in Half-Duplex Mode
    48
    
    MAC Address Checking
    48
    
    Frame Length/Type Checking
    50
    
    Payload Pad Removal
    52
    
    Frame Length Checking
    52
    
    CRC Checking
    53
    
    Receive FIFO Thresholds
    54
  - MAC Transmit Operation
    56
    
    MAC Address Insertion
    57
    
    Frame Payload Padding
    57
    
    CRC-32 Generation
    57
    
    Inter Packet Gap
    58
    
    Collision Detection in Half-Duplex Mode
    58
    
    Transmit FIFO Thresholds
    60
    
    Transmit FIFO Underflow
    61
    
    Transmit FIFO Overflow
    62
  - MAC Receive and Transmit FIFO Interfaces
    63
  - MAC Full Duplex Flow Control Operation
    64
    
    Remote Device Congestion
    64
    
    Local Device / FIFO Congestion
    65
    
    Pause Frames
    66
  - Magic Packet Detection
    67
    
    Sleep Mode
    68
    
    Magic Packet Detection
    68
    
    Wakeup
    68
  - Software Reset
    69
  - PHY Management (MDIO)
    70
    
    MDIO Frame Format
    71
    
    MDIO Registers
    72
    
    MDIO Clock Generation
    72
    
    MDIO Buffer Connection
    72
  - MAC Interface Register Map
    73
    
    Complete MAC Interface Register Map
    74
    
    Command_Config Register
    74
    
    Reg_Status Register
    76
    
    Tx_Cmd_Stat Register
    85
    
    Rx_Cmd_Stat Register
    86
    
    MAC SNMP MIB Statistics Registers
    87
  - MII, GMII and RGMII Interfaces
    91
    
    GMII Interface
    91
    
    RGMII Interface
    93
    
    MII Interface
    94
  - Connecting MAC to External PHY
    96
    
    Gigabit Ethernet
    97
    
    Programmable 10/100/1000 Operation
    98
- 1000BASE-X/SGMII PCS with Optional PMA
  100
  - PCS Receive
    101
    
    Comma Detection
    101
    
    8B/10B Decoding
    102
    
    Frame De-Encapsulation
    102
    
    Synchronization
    102
    
    Carrier Sense
    103
  - PCS Transmit
    103
    
    Frame Encapsulation
    103
    
    8B/10B Encoding
    103
  - SGMII Converter
    104
    
    Transmit
    104
    
    Receive
    104
    
    Clock Distribution with External PMA
    104
    
    Clock Distribution with Embedded PMA
    106
  - Auto-Negotiation
    107
    
    1000BASE-X Auto-Negotiation
    107
    
    SGMII Auto-Negotiation
    109
  - TBI Interface
    109
  - PHY Loopback
    110
  - PHY Power-Down
    110
    
    Power-Down with Embedded PMA
    111
  - PCS Control Interface Register Map
    112
    
    PCS Control Register
    114
    
    Status Register
    115
    
    Dev_Ability and Partner_Ability Registers
    116
    
    An_Expansion Register
    117
    
    If_Mode Register
    118
- Signals
  119
  - 10/100/1000 Ethernet MAC Signals
    119
    
    Control Interface Signals
    120
    
    MAC System-Side Signals
    121
    
    MAC Ethernet-Side Signals
    127
  - 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
    131
    
    Control Interface Signals
    132
    
    MAC System-Side Signals
    132
    
    PCS Ethernet-Side Signals
    132
  - 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and PMA Signals
    134
    
    Control Interface Signals
    135
    
    MAC System-Side Signals
    135
    
    PCS Ethernet-Side Signals
    135
  - 1000BASE-X/SGMII PCS Signals
    137
    
    Control Interface Signals
    138
    
    PCS MAC-Side Signals
    139
    
    PCS Ethernet-Side Signals
    141
  - 1000BASE-X/SGMII PCS and PMA Signals
    142
    
    Control Interface Signals
    142
    
    PCS MAC-Side Signals
    143
    
    PCS Ethernet-Side Signals
    143
Chapter 5. Testbench

145
- Introduction
  145
- Testbench Specifications
  145
  - Avalon-ST Ethernet Frame Generator
    145
  - Avalon-ST Ethernet Frame Monitor
    145
  - MII/RGMII/GMII Ethernet Frame Generator
    145
  - MII/RGMII/GMII Ethernet Frame Monitor
    145
  - MDIO Slave
    146
  - Configuration
    146
  - Verification
    147
- Testbench Architecture
  148
  - 10/100/1000 Ethernet MAC
    148
    
    Overview
    148
    
    Default Testbench Configuration
    149
    
    Test Flow
    149
  - 1000Base-X/Sgmii Pcs
    151
    
    Overview
    151
    
    Default Testbench Configuration
    151
    
    Test Flow
    152
  - 1000BASE-X/SGMII PCS with Embedded PMA
    153
    
    Overview
    153
    
    Default Testbench Configuration
    154
    
    Test Flow
    154
  - 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS
    155
    
    Overview
    155
    
    Default Testbench Configuration
    156
    
    Test Flow
    156
  - 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
    158
    
    Overview
    158
    
    Default Testbench Configuration
    159
    
    Test Flow
    159
Chapter 6. Software Programming Interface

161
- Triple Speed Ethernet Driver Architecture
  161
- Directory Structure
  163
- API Functions
  164
  - Triple_Speed_Ethernet_Init()
    164
  - Tse_Mac_Close()
    165
  - Tse_Mac_Raw_Send()
    166
  - Tse_Mac_Setgmii Mode()
    167
  - Tse_Mac_Setmiimode()
    168
  - Tse_Mac_Swreset()
    169
- Constants
  170
Appendix A. Simulation Parameters

173
- Functionality Configuration Parameters
  173
- Test Configuration Parameters
  180

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