Vertex Standard VX-920 Series Service Manual page 9

tector Q1072 (NJM12902V) is compared with the ref-
erence voltage and amplified by the power control
amplifier Q1072 (NJM12902V). The output from
Q1072 (NJM12902V) controls the gate bias of the fi-
nal amplifier Q1010 (2SK3476) and the driver Q1021
(2SK3475). The reference voltage switches among
four values of TX Power ("High," "Low3," "Low2,"
and "Low1"), as controlled by Q1020 (M62364FP).
3-5. PLL Frequency Synthesizer
The frequency synthesizer consists of PLL IC Q1070
(SA7025DK), the VCO, TCXO (X1003), and buffer
amplifier. The output frequency from the TCXO is
16.8 MHz, and the tolerance is ±2.5 ppm (in the tem-
perature range —30 °C to +60 °C).
3-5-1. VCO (Voltage-Controlled Oscillator)
While the radio is receiving, the RX oscillator Q1047
(2SK508) in the VCO generates a programmed fre-
quency between 184.85 and 224.85 MHz as the 1st
local signal. While the radio is transmitting, the TX
oscillator Q1052 (2SC4227) in the VCO generates a
frequency between 134 and 174 MHz (the actual
transmitting frequency). The output from the oscil-
lator is amplified by buffer amplifier Q1042
(2SC5226) and becomes the output of the VCO. The
output from VCO is divided: one part is amplified
by Q1051 (2SC5226) and fed back to the PLL IC at
pin 5. The other is amplified by Q1033 (2SC5226)
and, in case of the reception, it is fed via D1020
(DAN222) to the mixer as the 1st local signal. On
transmit, it is buffered Q1027 (2SC3356), and passed
through D1020 (DAN222) to amplifier Q1021
(2SK2375) and then fed to the final amplifier Q1010
(2SK2376).
3-5-2. VCV (Varactor Control Voltage) Control
The tuning voltage (VCV) of the VCO establishes
the lock range of the VCO by controlling the anode
of a varactor diode using a negative voltage and the
Circuit Description
control voltage from PLL IC Q1070 (SA7025DK). The
negative voltage is fed to the varactor diode after
c o n ve r s i o n t o a n e g a t i ve va l u e a t Q 1 0 3 1
(NJM2130F), using the output voltage of the D/A
converter, Q1020 (M62364FP).
3-5-3. PLL
The PLL IC Q1070 (SA7025DK) consists of a refer-
ence divider, main divider, phase detector, charge
pumps and a fractional accumulator. The reference
frequency from TCXO is applied to pin 8 of the PLL
IC Q1070 (SA7025DK) and is divided by the refer-
ence divider. This IC is a decimal point dividing PLL
IC, and the dividing ratio becomes 1/8 of the usual
PLL frequency step. Therefore, the output of refer-
ence divider is 8 times the frequency of the channel
step. For example, when the channel steps are set to
5 kHz, the output of reference divider becomes 40
kHz. The feedback signal from the VCO applied to
5 pin of the PLL IC Q1070 (SA7025DK) is divided
according to the dividing ratio so as to become the
same frequency as that of the output of reference
divider. These two signals are compared by the
phase detector, and a phase difference pulse is gen-
erated. The phase difference pulse and the pulse
from the fractional accumulator pass through the
charge pumps and low-pass filter, producing a DC
voltage (VCV) to control the VCO. The oscillation
frequency of the VCO is therefore locked via the
control of this DC voltage. The PLL serial data from
the CPU Q1069 (LC87F5BP6A) is sent with three
lines of data: SDO (pin 20), SCK (pin 22) and PSTB
(pin 27). The lock condition of the PLL is sent from
the UL (pin 17) terminal, and UL becomes "High"
at the time of a proper lock condition and becomes
"Low" at the time of an unlocked condition. The
CPU always watches over the UL condition, and
when it becomes "Low" (unlocked condition), the
CPU Q1069 (LC87F5BP6A) prohibits transmission
and reception.
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