Marantz SR6003 Service Manual page 96

Aureus™ family of high-performance 32-/64-bit floating-point digital signal processors.
Note: The TMS320DA788B supports DTS® 5.1, DTS-ES™ 6.1, DTS Neo:6™, DTS 96/24™, and DTS-ES
96/24™. If the application requires DTS algorithms, the TMS320DA788B DSP should be used.
Figure 2-1 illustrates a high-level block diagram of the device and other devices to which it may typically
IC21 : TMS320DA788B
connect. An overview of each major block follows the figure.
C67x+
DSP Core
Program
Cache
Crossbar Switch
EMIF
ASYNC
FLASH
100-MHz/
www.ti.com
133-MHz
SDRAM
2.15 Device Block Diagram
Figure 2-1. DA708/B/DA788B Aureus™ Audio DSP System Diagram
2.1 Enhanced C67x+ CPU
The C67x+ CPU is an enhanced version of the C67x CPU used on the DA6xxx first-generation Aureus™
DSP. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and
C67x+ CPU
floating-point performance per clock cycle. At 266 MHz, the CPU is capable of a maximum performance of
2128 MIPS/1596 MFLOPS by executing up to eight instructions (six of which are floating-point
instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision
floating-point, and 64-bit double-precision floating-point arithmetic.
Program
I/O INT
2.2 Efficient Memory System
The memory controller maps the large on-chip 256K-byte RAM and 768K-byte ROM as unified
program/data memory. Development is simplified since there is no fixed division between program and
Program
data memory size as on some other devices.
Cache
The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.
32K Bytes
Up to four simultaneous accesses are supported:
4 Device Overview
I/O Interrupts
Out
DSP
McASP0
256K
Bytes
SPI1
RAM
I2C0
McASP1
768K
Bytes McASP2
ROM
SPIO
I2C1
dMAX
PLL
Host
Microprocessor
D1
Data 64
R/W
D2
Memory
Data 64
Controller
R/W
Fetch
CSP
256
PMP DMP
32 32
High-Performance
Crossbar Switch
32 32 32
MAX0 CONTROL MAX1
dMAX
Figure 2-3. DA708/B/DA788B DSP Block Diagram
Audio Zone 1
SPI or I2C
Control (optional)
Audio Zone 2
Audio Zone 3
RTI
OSC
DSP Control
SPI or I2C
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B
Program/Data
256 RAM
256K Bytes
Program/Data
256 ROM Page1
256K Bytes
Program/Data
256 ROM Page2
256K Bytes
Program/Data
256 ROM Page3
256K Bytes
32
32
Events
In
EMIF
124
CODEC, DIR,
ADC, DAC, DSD,
CODEC, DIR,
ADC, DAC, DSD,
Digital Out
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins
Floating-Point Digital Signal Processors
SPRS297E – JULY 2005 – REVISED JULY 2007
JTAG EMU
32
32
32
32
32
32
32
32
32
32
Submit Documentation Feedback
32
32
32
32
Peripheral Interrupt and DMA Events
Network
Network
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
DIT Only
SPI1
SPI0
I2C0
I2C1
RTI
PLL