Marantz SR6003 Service Manual page 105

IC41 : IP00C773 (IPSD2)
IP00C773
CHAPTER 3 INTERNAL CONFIGURATION
3.1 Block Diagram
MCS*
MRAS*
MCAS*
MWR*
MDQM[3:0] BA[1:0]
Image input
port signal
Image input block
Write image data
20
PID[19:0]
Temporal
filter
Image input
timing signal
IP
conversion
PIVS*
PIHS*
PIFLD
Image input
PIACT* timing control
circuit
DB[7:0]
(Note) This block diagram simply shows the outline of IP00C773's internal structure and does not describe
2.2 Pin Description
Group Designation
Image input port PID[19:0]
PICLK
PIVS*
PIHS*
PIFLD
PIACT*
Image output port POD[29:0]
POCLK
POVS*
POHS*
POFLD
POACT*
POOSDACT[1:0]
POCLKO
POEN*
POEXT*
Image memory BA[1:0]
interface
MA[11:0]
MD[31:0]
MCS*
MRAS*
MCAS*
MWR*
MDQM[3:0]
Memory clock MCLK
MCLKO
MCLKRT
MCLKSEL[1:0]
CPU SYSCLK
interface
AD
DB[7:0]
WE*
RE*
CE*
WAIT*
IFMD
I2C slave SCL
SDA
RST*
TEST*[1:0]
TESTH
XTEST
Power supply / GND VDDE
VDDI
PLLVDD
VSS
PLLVSS
Image memory interface signal
Total No. of pins
(Note 1) Designation marked with an asterisk (*) denotes negative logic.
(Note 2) All grounds must be connected to GND and power supply to VDD.
Image memory Image memory
(Note 3) Since the LSI is CMOS device, leaving the input pins floating may cause undesirable operation. Pull up or down all
address data
MA[11:0]
the unused input pins.
MD[31:0] MCLKO
32
Image memory interface block
i-Chips Technology Inc.
Internal bus
control block
CPU interface block
SYSCLK RST* AD
WE*,RE*,CE*
CPU Interface signal
No. of
I/O
pins
20 I Image input port
1 I Image input clock input
1 I Image input vertical sync signal
1 I Image input horizontal sync signal
1 I Image input field signal
1 I Digital interface
30 O Image output port
1 I Image output clock input
1 I/O Image output vertical sync signal
1 I/O Image output horizontal sync signal
1 I/O Image output field signal
L: Image output target area
1 O
H: Out of image output target area
2 O OSD transparent/active area signal
1 O Image output clock output
1 I Image output port enable signal
1 I Image output port external sync enable signal
2 O Image memory bank signal
12 O Image memory address bus
32 I/O Image memory data bus
1 O Image memory chip select
1 O Image memory low address strobe
1 O Image memory column address strobe
1 O Image memory write signal
4 O Image memory data mask signal
1 I Image memory clock
1 O Image memory clock output
1 I Image memory clock return input
2 I Image memory clock select
1 I System clock
1 I Address bus
8 I/O Data bus
1 I Write enable
1 I Read enable
1 I Chip enable
1 O Wait
1 I Interface mode
1 I/O I2C buffer
1 I/O I2C buffer
1 I Reset signal
2 I Test signal - High level usually
1 I Test signal - Low level usually
1 I Test signal - Low level usually
22 PWR Power supply (3.3 V)
14 PWR Power supply (1.8 V)
2 PWR PLL power supply (1.8 V)
22 PWR Ground
2 PWR PLL ground
208
MCLK
MCLKRT
Image output
port signal
Image output block
30
Read image data
Picture
quality POD[29:0]
adjustment
Enlargement POCLK
Image output
timing signal
Image output
timing control
POVS* POHS*
circuit
POFLD
POACT*
POOSDACT[1:0]
POCLKO
SCL,SDA
133
IP00C773
Function Remarks
Clock buffer
8 mA,Tri-state
Clock buffer
8 mA,Bi-Dir
8 mA,Bi-Dir
8 mA,Bi-Dir
8 mA,Tri-state
8 mA,Tri-state
8 mA,Tri-state
schmitt
schmitt
4 mA
4 mA
8 mA,pull up
8 mA
4 mA
4 mA
4 mA
8 mA
Clock buffer
8 mA
Clock buffer
schmitt
schmitt
3.3 V CMOS
4 mA,Bi-Dir
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
4 mA,Tri-state
schmitt
I2C buffer
I2C buffer
schmitt
schmitt
3.3 V CMOS Pull-down
5