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Summary of Contents for Supero SUPER S2DG2
- Page 1 ® UPER SUPER S2DG2 SUPER S2DGU SUPER S2DGE SUPER S2DGR USER’S AND BIOS MANUAL Revision 1.3...
- Page 2 The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this Please Note: For the manual, or to notify any person or organization of the updates.
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Page 3: Manual Organization
This manual is written for system houses, PC technicians and knowledgeable PC end users. It provides information for the installation and use of the SUPER S2DG2/S2DGU/S2DGE/S2DGR motherboard. The SUPER S2DG2/S2DGU/S2DGE/S2DGR supports Pentium II and III Xeon processors. The Pentium II/III Xeon processor with the Dual Independent Bus Architecture is based on the "Slot 2"... - Page 4 User’s Manual S2DG2/S2DGU/S2DGE/S2DGR Chapter 5 has information on running setup and includes the default settings for Standard Setup, Advanced Setup, Chipset Function, Power Management, PCI/PnP Setup and Peripheral Setup. Appendix A offers information on BIOS error beep codes and messages. Appendix B shows post diagnostic error messages.
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Page 5: Table Of Contents
Front Control Panel Headers ..................ix Chapter 1: Introduction Overview ......................1-1 SUPER S2DG2 Image ................1-2 SUPER S2DG2 Motherboard Layout ............. 1-3 SUPER S2DGU Image ................1-4 SUPER S2DGU Motherboard Layout ............. 1-5 SUPER S2DGE Image ................1-6 SUPER S2DGE Motherboard Layout ............. 1-7 SUPER S2DGR Image ................ - Page 6 User’s Manual S2DG2/S2DGU/S2DGE/S2DGR Explanation and Diagram of Jumper/Connector ........2-4 Changing the CPU Speed ................2-4 Mounting the Motherboard in the Chassis ..........2-5 Connecting Cables ..................2-5 Power Supply Connectors ..............2-5 Secondary Power Connector ..............2-5 Infrared Connector ..................2-5 PW_ON Connector ..................
- Page 7 Table of Contents Memory Errors ..................3-2 Losing the System’s Setup Configuration ..........3-3 Technical Support Procedures ..............3-3 Frequently Asked Questions ................. 3-4 Returning Merchandise for Service ............. 3-7 Chapter 4: AMIBIOS Introduction ....................... 4-1 BIOS Features ....................4-2 BIOS Configuration Summary Screen ...........
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Page 8: Jumper Quick Reference
User’s Manual S2DG2/S2DGU/S2DGE/S2DGR Jumper Quick Reference S2DG2/S2DGR S2DGU/S2DGE* Jumpers Function Page Jumpers Function Page JB1, JB2, JB3, JB4 CPU Core/Bus Ratio Selection CPU Core/Bus Ratio Selection JB1, JB2, JB3, JB4 J B T 1 C M O S C l e a r C M O S C l e a r J B T 1 J P 2 0... -
Page 9: Front Control Panel Headers
Front Control Panel Front Control Panel Headers JF2 JF1 H a r d Drive LED IR Con P o w e r L E D K e y b o a r d lock P o w e r O n S p e a k e r R e s e t See pages 2-5 through 2-7 for... - Page 10 Preface Notes...
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Page 11: Chapter 1: Introduction
Chapter 1 Introduction Overview The SUPER S2DG2/S2DGU/S2DGE/S2DGR supports dual Pentium II Xeon™ and dual Pentium III Xeon processors. All four motherboards are based on Intel’s 440GX chip set, which supports a 100 MHz system bus speed, an Accelerated Graphics Port (AGP), Wake-on-LAN™, SDRAM, concurrent PCI and a 33 MB/s Ultra DMA burst data transfer rate. -
Page 12: Super S2Dg2 Image
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DG2 Figure 1-1. SUPER S2DG2 Motherboard Image... -
Page 13: Super S2Dg2 Motherboard Layout
2-3 BIOS CTL PD State (default) Note: JA3 is optional. WOL: Wake-On-LAN JA5: SCSI Termination for JA1 Note: To enable the overheat buzzer, place a jumper JA6: SCSI Termination for JA3 JA7: SCSI Termination for JA2 on BZ_ON. ——–———————–——–—–——–——–— Figure 1-2. SUPER S2DG2 Motherboard Layout... -
Page 14: Super S2Dgu Image
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGU Figure 1-3. SUPER S2DGU Motherboard Image... -
Page 15: Super S2Dgu Motherboard Layout
Chapter 1: Introduction 9.65" J 3 4 PS/2 KB P S / 2 MOUSE J17, J18 U S B BZ_ON J O H Overheat J 1 9 L E D P a r a l l e l Port JP_WP JP16 JP20 JP11... -
Page 16: Super S2Dge Image
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGE Figure 1-5. SUPER S2DGE Motherboard Image... -
Page 17: Super S2Dge Motherboard Layout
Chapter 1: Introduction 9.65" J 3 4 PS/2 KB P S / 2 MOUSE J17, J18 U S B BZ_ON J O H Overheat J 1 9 L E D P a r a l l e l JP_WP Port JP16 12"... -
Page 18: Super S2Dgr Image
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGR Figure 1-7. SUPER S2DGR Motherboard Image... -
Page 19: Super S2Dgr Motherboard Layout
Chapter 1: Introduction 9.6" JP13 JP12 J 3 4 PS/2 P S / 2 MOUSE J17, J18 U S B J 1 9 P a r a l l e l Port JP_WP BZ_ON JT2A JTA3 1 JOH1 JP16 PCI 4 J T M JP20 JP18... -
Page 20: 440Gx Agp Chip Set: System Block Diagram
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR C P U C P U Host Bus S D R A M A G P 440GX Port PCI Slots SMBus APIC PIIX4 IDE Ports Power SCSI Management U S B U S B Ports ISA Slots BIOS Figure 1-9. - Page 21 Chapter 1: Introduction Features of the S2DG2, S2DGU, S2DGE and S2DGR Motherboards* * Bold text indicates variations in features. The following list covers the general features of the S2DG2, S2DGU, S2DGE and S2DGR motherboards. • Dual Pentium II Xeon and dual Pentium III Xeon processors at 100 MHz bus speed Memory •...
- Page 22 • BIOS Flash Upgrade Utility • SUPER Doctor Utility • SCSI Utility, manual and driver Dimensions • SUPER S2DG2 - ATX (12" x 10.65") *See board diagram for full measurements. • SUPER S2DGU - ATX (12" x 9.65") *See board diagram for full measurements.
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Page 23: Chip Set Overview
L2 cache that can run at full CPU speed. PC Health Monitoring This section describes the PC health monitoring features of the SUPER S2DG2/ S2DGU/S2DGE/S2DGR. All have an onboard System Hardware Monitor chip that supports PC health monitoring. - Page 24 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Three-Fan Status Monitors with Firmware/Software On/Off Control The PC health monitor can check the RPM status of the cooling fans. The thermal fans are controlled by the overheat detection logic. Please Note: The tachometer readings are for JT1, JT2 and JT3 only .
- Page 25 Chapter 1: Introduction System Resource Alert This feature is available when used with Intel's LANDesk Client Manager. It is used to notify the user of certain system events. For example, if the system is running low on virtual memory and there is insufficient hard drive space for saving the data, you can be alerted of the potential problem.
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Page 26: Acpi/Pc 98 Features
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR ACPI/PC 98 Features ACPI stands for Advanced Configuration and Power Interface. The ACPI speci- fication defines a flexible and abstract hardware interface that provides a stan- dard way to integrate power management features throughout a PC system, including hardware, the operating system and application software. -
Page 27: Power Supply Requirements
This is even more important for the 400 MHz and higher clock rates of Xeon processors. The SUPER S2DG2/S2DGU/S2DGE/S2DGR accommodates ATX power sup- plies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. -
Page 28: Super I/O
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR computer from noise. It is recommended that you also install a power surge protector to help avoid problems caused by power surges. Super I/O The disk drive adapter functions of the Super I/O chip include a floppy disk drive... -
Page 29: Aic 7890 Scsi Controller
Chapter 1: Introduction AIC-7890 Ultra2 SCSI Controller (S2DGU) Note: If you are using a low voltage differential hard drive, it is recommended that you use an LVD/SE Ultra2 SCSI cable. LVD/SE cables offer increased length and can accommodate up to 15 devices. - Page 30 SUPER S2DG2/S2DGU/S2DGE/S2DGR 1-10 AIC-7896 Ultra2 Dual Channel SCSI Controller (S2DG2) The SUPER S2DG2 has an onboard Adaptec SCSI controller that is 100% com- patible with all major operating and hardware platforms. PCI 2.1 compliance is assured. The AIC-7896 Ultra2 SCSI chip connects to a 32-bit PCI bus. Two independent Ultra2 LVD SCSI channels provide a per channel data transfer rate of 80 MB/s.
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Page 31: 1-11 Warranty, Technical Support And Service
Chapter 1: Introduction 1-11 Warranty, Technical Support and Service The manufacturer will repair or exchange any unit or parts that fail due to manu- facturing defects. This warranty covers the cost of parts for one year (12 months) and the cost of labor for two years (24 months) from the original invoice date of purchase. - Page 32 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Notes 1-22...
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Page 33: Chapter 2: Installation
Chapter 2: Installation Chapter 2 Installation Static-Sensitive Devices Static-sensitive electrical discharge can damage electronic components. To prevent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from static discharge. -
Page 34: Removing The Pentium Ii/Iii Xeon Processor
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Installing the metal standoffs: Attach the metal standoffs to the back of the motherboard tray. Be sure the location of all the mounting holes for both the motherboard and the chassis match. Make sure the metal standoffs click in or are screwed in tightly. - Page 35 Chapter 2: Installation Figure 2-1. Dual Retention Module Mounting holes When mounting the motherboard to the chassis, please note ATX Standard Extra for there are three holes Hole Slot 2 specifically for mounting the Slot 2 DRM as well as an Extra for Slot 2 Extra for Slot 2 ATX Standard hole...
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Page 36: Explanation And Diagram Of Jumper/Connector
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Explanation and C o n n e c t o r Diagram of Jumper/ Pins Connector To modify the operation of the moth- J u m p e r C a p erboard, jumpers can be used to choose between optional settings. -
Page 37: Mounting The Motherboard In The Chassis
Chapter 2: Installation Mounting the Motherboard in the Chassis All the motherboards have standard mounting holes to fit different types of chas- sis. Chassis may come with a variety of mounting fasteners made of metal or plastic. Although a chassis may have both metal and plastic fasteners, metal fasteners are the most highly recommended because they ground the system board to the chassis. -
Page 38: Pw_On Connector
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR PW_ON Connector The header for the PW_ON connec- Table 2-5 PW_ON Header tor is located on pins 9 and 10 of JF2. Momentarily contacting both pins will power on/off the system. N u m b e r... -
Page 39: Speaker Connector
Chapter 2: Installation Table 2-9 Speaker Connector Speaker Header The header for the speaker connec- N u m b e r Function Definition tor is located on pins 10 to 13 of JF1. Red wire, Speaker data K e y No connection See Table 2-9 for pin definitions. -
Page 40: Atx Serial Ports
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Table 2-13 ATX Serial Ports ATX Serial Ports ATX serial port COM1 is located Pin Number Definition Pin Number Definition D C D C T S on J20 and serial port COM2 is D S R D T R Serial In located on J21. -
Page 41: Chassis Intrusion
Chapter 2: Installation Chassis Intrusion Table 2-18 Chassis Intrusion The Chassis Intrusion Detector is located on JL1. See the board lay- outs in Chapter 1 and the PC Health N u m b e r Definition Intrusion Input Monitor information on page 1-14 for G r o u n d more information. - Page 42 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Side View of DIMM Installation into Socket PC100 PC100 To Install: Notches Notches Insert DIMM vertically and press down until it snaps into place. Note: Notches should align Pay attention with their to the two receptive points on the socket notches.
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Page 43: Parallel Port Connector
Chapter 2: Installation hard disk drives and the SCSI adapter. (Note: Most SCSI hard drives are single-ended SCSI devices.) The SCSI ID is determined either by jumpers or by a switch on the SCSI device. The last internal (and external) SCSI device cabled to the SCSI adapter must be terminated. -
Page 44: Scsi Connectors
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Table 2-22 Ultra Wide SCSI Connector Pin Number Function Pin Number Function G N D -DB (12) G N D -DB (13) G N D -DB (14) G N D -DB (15) G N D Parity H... -
Page 45: Ultra2 Lvd/Se Scsi Connector
Chapter 2: Installation Table 2-24 Ultra2 LVD/SE SCSI Connector Connector Connector Contact Contact N u m b e r Signal Names N u m b e r Signal Names +DB(12) -DB(12) +DB(13) -DB(13) +DB(14) -DB(14) +DB(15) -DB(15) +DB(P1) -DB(P1) +DB(0) -DB(0) +DB(1) -DB(1) -
Page 46: Agp Port
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Table 2-25 AGP Port J8 Pin # Pin # Spare 1 2 V Vddq3.3 Vddq3.3 5.0V Spare A D 2 1 A D 2 2 5.0V Reserved* A D 1 9 A D 2 0 U S B +... -
Page 47: Chapter 3: Troubleshooting
Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures and chart to troubleshoot your system. If you have followed all the procedures below and still need assistance, refer to the ‘Tech- nical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. -
Page 48: No Power
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR No Power Make sure that the default jumper is on and the CPU is correctly set up. Turn the power switch on and off to test the system. If the power is still not on, turn the system power off and change the jumper setting on JP20 from 2-3 to 1-2. -
Page 49: Losing The System's Setup Configuration
Chapter 3: Troubleshooting Losing the System’s Setup Configuration Check the setting of jumper JBT1. Ensure that you are using a high quality power supply. A poor quality power supply may cause the system to lose the CMOS setup. Refer to Chapter 1 of this manual for details. -
Page 50: Frequently Asked Questions
Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Frequently Asked Questions Question: Do I need to change any settings to use a single processor on a dual processor board? Answer: There are no jumpers or BIOS settings that need to be changed when running a single CPU on a dual processor board. Also, you can use a single processor in either slot. - Page 51 Question: I have memory problems. What is the correct memory to use and which BIOS setting should I choose? Answer: The correct memory to use for the SUPER S2DG2/S2DGU/S2DGE/ S2DGR is 168-pin DIMMs of 3.3v non-buffered SPD (Serial Present Detection) SDRAM and SDRAM.
- Page 52 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Question: Do I need the CD that came with your motherboard? Answer: The supplied compact disc has quite a few drivers and programs that will greatly enhance your system. We recommend that you review the CD and install the applications you need.
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Page 53: Returning Merchandise For Service
Chapter 3: Troubleshooting Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA number should be prominently displayed on the outside of the shipping carton and either mailed prepaid or hand-carried. - Page 54 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Notes...
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Page 55: Chapter 4: Amibios
Chapter 4: AMIBIOS Chapter 4 AMIBIOS Introduction This chapter describes the AMIBIOS for Intel 440GX Pentium II/III Xeon proces- sors. The AMI ROM BIOS is stored in the Flash EEPROM and can be easily upgraded using a floppy disk-based program. System BIOS ®... -
Page 56: Bios Features
BIOS User's Manual American AMIBIOS (c) 1997 American Megatrends, Inc. M e g a Trends 0404981500 Pentium II Motherboard Made in USA R1.0 U P E R BIOS date code Checking NVRAM xxxxx KB OK BIOS revision code Hit <DEL> if you want to run SETUP (C) Super Micro Computer, Inc., XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X BIOS Features... -
Page 57: Bios Configuration Summary Screen
Chapter 4: AMIBIOS • Five positive voltage inputs • Two negative voltage inputs • Three fan speed monitor inputs BIOS Configuration Summary Screen AMIBIOS displays a screen that looks similar to the following when the POST routines complete successfully. AMIBIOS System Configuration (C) 1985-1997 American Megatrends Inc., Main Processor : Pentium(tm) II Base Memory Size... -
Page 58: Standard Cmos Setup
BIOS User's Manual Figure 4-1. AMIBIOS Hiflex Setup Utility Screen AMIBIOS Hiflex Setup Utility - Version 1.18 (C)1998 American Megatrends, Inc. All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Power Management Setup PCI / Plug and Play Setup Peripheral Setup Auto-Detect Hard Disks Change User Password... - Page 59 Chapter 5: Running Setup Chapter 5 Running Setup Optimal and Fail-Safe default settings are in bold text unless otherwise noted. The AMIBIOS Hiflex Setup options described in this section are selected by choosing the appropriate high-level icon from the Standard Setup screen. All displayed icons are described in this section, although the screen display is often all you need to understand how to set the options.
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Page 60: Boot Sector Virus Protection
BIOS User's Manual T y p e How to Configure 1-46 Predefined types. U S E R Enter parameters manually. A U T O Set parameters automatically on each boot. C D R O M Use for ATAPI CDROM drives. A R M D Use for LS120, MO, IOMEGA Zip drives. - Page 61 Chapter 5: Running Setup 5-1-2 Advanced CMOS Setup Quick Boot The Settings are Disabled or Enabled . Set to Enabled to permit AMIBIOS to boot quickly when the computer is powered on. This option replaces the old The settings are: Above 1 MB Memory Test Advanced Setup option.
- Page 62 BIOS User's Manual HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD, ATAPI CD ROM, SCSI, Network or I 0 . The options for the 2nd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM . The options for the 3rd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE- HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM .
- Page 63 Chapter 5: Running Setup Keep Current . If selected as Force BIOS, the POST will force the display to be changed to BIOS mode before giving control to any add-on ROM. If no add-on ROM is found, then the current display mode will remain unchanged even if this setup question is selected as Force BIOS.
- Page 64 BIOS User's Manual CPU Microcode Updation Set this option to Enabled to permit the CPU to be updated on line. The settings for this option are Enabled or Disabled . Internal Cache This option is for enabling or disabling the internal cache memory. The settings for this option are Disabled , Write-thru or WriteBack .
- Page 65 Chapter 5: Running Setup adapter cards. The settings are: Disabled , Enabled or Cached . When set to Disabled, the contents of the video ROM are not copied to RAM. When set to Enabled, the contents of the video ROM area from C0000h-C7FFFh are copied (shadowed) from ROM to RAM for faster execution.
- Page 66 BIOS User's Manual PERR# The settings for this option are Enabled or Disabled . Set to Enabled to enable the PERR# signal on the bus. WSC# Handshake (Write Snoop Complete) This signal is asserted active to indicate that all the snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is complete and that it is safe to send the APIC interrupt message.
- Page 67 Chapter 5: Running Setup Setting Description None No error checking or error reporting is done. Multibit errors are detected and reported as parity errors. Single-bit errors are corrected by the chipset. Corrected bits of data from memory are not written back to DRAM system memory. Multibit errors are detected and reported as parity Hardware errors.
- Page 68 BIOS User's Manual SDRAM RAS# to CAS# Delay This option specifies the length of the delay inserted between the RAS and CAS signals of the DRAM system memory access cycle if SDRAM is installed. The settings are Auto (AMIBIOS automatically determines the optimal delay), 2 SCLKs or 3 SCLKs .
- Page 69 Chapter 5: Running Setup AGP Multi-Trans Timer (AGP Clks) This option sets the AGP multi-trans timer. The settings are in units of AGP clocks: 32 , 64 , 96 , 128 , 160 , 192 , or 224 . AGP Low-Priority Timer This option controls the minimum tenure on the AGP for low priority data transaction for both read and write.
- Page 70 BIOS User's Manual PIIX4 Delayed Transaction GX is capable of PIIX4 transaction to improve PIIX4 interrupt efficiency. The settings for this option are Enabled or Disabled . Set this option to Enabled to enable delayed transactions for the Intel PIIX4 chip. Type F DMA Buffer Control1 Type F DMA Buffer Control2 These options specify the DMA channel where Type F buffer control is...
- Page 71 Chapter 5: Running Setup to On/Off , pushing the power button turns the computer on or off. When set to Suspend , pushing the power button places the computer in Suspend mode or Full On power mode. Green PC Monitor Power State This option specifies the power state that the green PC-compliant video monitor enters when AMIBIOS places it in a power savings state after the specified period of display inactivity has expired.
- Page 72 BIOS User's Manual Suspend Timeout (Minutes) This option specifies the length of a period of system inactivity while in standby state. When this length of time expires, the computer enters suspend power state. The settings are Disabled and 4 Min through 508 Min in 4 minute intervals .
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Page 73: Pci/Pnp Setup
Chapter 5: Running Setup 5-1-5 PCI/PnP Setup Plug and Play-Aware OS The settings for this option are No or Yes . Set this option to Yes if the operating system in the computer is aware of and follows the Plug and Play specification. - Page 74 BIOS User's Manual This option forces IRQ14 and IRQ15 to a PCI slot on the PCI local bus. This is necessary to support non-compliant ISA IDE controller adapter cards. If an offboard PCI IDE controller adapter card is installed in the computer, you must also set the Offboard PCI IDE Primary IRQ and Offboard PCI IDE Secondary IRQ options.
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Page 75: Peripheral Setup
Chapter 5: Running Setup removed from the pool, the end user can use these options to reserve the IRQ by assigning an ISA/EISA setting to it. Onboard I/O is configured by AMIBIOS. All IRQs used by onboard I/O are configured as PCI/PnP. IRQ14 and 15 will not be available if the onboard PCI IDE is enabled. - Page 76 BIOS User's Manual System Overheat Warning The settings for this option are Enabled or Disabled . When set to Enabled, this option allows the user to set an overheat warning temperature. Set Overheat Warning Temperature Use this option to set the overheat warning temperature. The settings are 25°C through 99°C in 1°C intervals .
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Page 77: Auto Detect Hard Disks
Chapter 5: Running Setup On-Board Parallel Port This option specifies the base I/O port address of the parallel port on the motherboard. The settings are Auto (AMIBIOS automatically determines the correct base I/O port address), Disabled , 378 , 278 or 3BC . Parallel Port Mode This option specifies the parallel port mode. -
Page 78: Change Language Setting
BIOS User's Manual Pri Master Pri Slave Sec Master Sec Slave Select these options to configure the drive named in the option. The setting for Primary Master and Secondary Slave is Auto . The Primary Slave and Secondary Master are Not-Installed . Change User Password Change Supervisor Password The system can be configured so that all users must enter a password every... -
Page 79: Default Settings
Chapter 5: Running Setup Default Settings Every option in AMIBIOS Hiflex Setup contains two default settings: a Fail- Safe default, and an Optimal default. 5-5-1 Auto Configuration with Optimal Settings The Optimal default settings provide optimum performance settings for all devices and system features. - Page 80 BIOS User's Manual Notes 5-22...
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Page 81: Appendix A: Bios Error Beep Codes And Messages
Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes & Messages During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. - Page 82 BIOS User’s Manual Beeps Error message Description Refresh Failure The memory refresh circuitry on the motherboard is faulty. Parity Error A parity error was detected in the base memory (the first 64 KB block) of the system. Base 64 KB Memory Failure A memory failure occurred within the first 64 KB of memory.
- Page 83 Appendix A: BIOS Error Beep Codes If it beeps... then ... 1, 2 or 3 times reseat the DIMM memory. If the system still beeps, replace the memory. 6 times reseat the keyboard controller chip. If it still beeps, replace the keyboard controller.
- Page 84 BIOS User’s Manual Error Message Information 8042 Gate -- A20 Gate A20 on the keyboard controller (8042) Error is not working. Replace the 8042. Address Line Short! Error in the address decoding circuitry on the motherboard. C: Drive Error Hard disk drive C: does not respond. the Hard Disk Utility to correct this problem.
- Page 85 Appendix A: BIOS Error Beep Codes Error Message Information CMOS Time and Run Standard Setup to set the date and time Date Not Set in CMOS RAM. D: Drive Error Hard disk drive D: does not respond. the Hard Disk Utility. Also check the D: hard disk type in Standard Setup to make sure that the hard disk drive type is correct.
- Page 86 BIOS User’s Manual Error Message Information Invalid Boot Diskette The BIOS can read the disk in floppy drive A:, but cannot boot the computer. Use another boot disk. Keyboard Is Locked... The keyboard lock on the computer is Unlock It engaged.
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Page 87: Appendix B: Amibios Post Diagnostic Error Messages
Appendix B: AMIBIOS POST Diagnostics Error Messages Appendix B AMIBIOS POST Diagnostic Error Messages This section describes the power-on self-tests (POST) port 80 codes for the AMI BIOS. Check PointDescription Code copying to specific areas is done. Passing control to INT 19h boot loader next. NMI is Disabled. - Page 88 BIOS User’s Manual Check PointDescription The keyboard controller command byte is written. Next, issuing the pin 23 and 24 blocking and unblocking commands. Next, checking if the <End or <Ins> keys were pressed during power Initializing CMOS Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the <End>...
- Page 89 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next. Bus initialization system, static, output devices will be done next, if present. Passing control to the video ROM to perform any required configuration before the video ROM test.
- Page 90 BIOS User’s Manual Check PointDescription Initializing the bus input, IPL, and general devices next, if present. Displaying bus initialization error messages. The new cursor position has been read and saved. Displaying the Hit <DEL> message next. Preparing the descriptor tables next. The descriptor tables are prepared.
- Page 91 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next. The memory above 1 MB has been cleared via a soft reset. Saving the memory size next.
- Page 92 BIOS User’s Manual Check PointDescription The DMA page register test passed. Performing the DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
- Page 93 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription programming before WINBIOS Setup been completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next. Returned from WINBIOS Setup and cleared the screen. Performing any necessary programming after WINBIOS Setup next.
- Page 94 BIOS User’s Manual Check PointDescription Any initialization required after the option ROM test has been completed. Configuring the timer data area and printer base address next. Set the timer and printer base addresses. Setting the RS-232 base address next. Returned after setting RS-232...
- Page 95 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription Returned from adaptor E000h control. Next, performing initialization required after the E000 option ROM had control. Initialization after E000 option control completed. Displaying the system configuration next. Building the multiprocessor table, if necessary. POST next.
- Page 96 BIOS User’s Manual If either <Ctrl><Home> was pressed or the system BIOS checksum is bad, the system will next go to checkpoint code E0h. Otherwise, going to checkpoint code D7h. B-10...
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