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Supero SUPER S2DG2 User's And Bios Manual

Supermicro s2dg2 motherboards: user guide
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UPER
SUPER S2DG2
SUPER S2DGU
SUPER S2DGE
SUPER S2DGR
USER'S AND BIOS
MANUAL
Revision 1.4

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  • Page 1 UPER SUPER S2DG2 SUPER S2DGU SUPER S2DGE SUPER S2DGR USER’S AND BIOS MANUAL Revision 1.4...
  • Page 2 SUPERMICRO COMPUTER reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent.

  • Page 3: About This Manual

    Manual Organization Chapter 1, Introduction, describes the features, specifications and perfor- mance of the SUPER S2DG2/S2DGU/S2DGE/S2DGR system board and pro- vides detailed information about the chipset. Refer to Chapter 2, Installation, for instructions on how to install the Pentium II/III Xeon processor, the retention mechanism and the heat sink support.
  • Page 4 User’s Manual S2DG2/S2DGU/S2DGE/S2DGR Chapter 5 has information on running setup and includes the default settings for Standard Setup, Advanced Setup, Chipset Function, Power Management, PCI/PnP Setup and Peripheral Setup. Appendix A offers information on BIOS error beep codes and messages.

  • Page 5: Table Of Contents

    Front Control Panel Headers ... ix Chapter 1: Introduction Overview ... 1-1 SUPER S2DG2 Image ... 1-2 SUPER S2DG2 Motherboard Layout ... 1-3 SUPER S2DGU Image ... 1-4 SUPER S2DGU Motherboard Layout ... 1-5 SUPER S2DGE Image ... 1-6 SUPER S2DGE Motherboard Layout ... 1-7 SUPER S2DGR Image ...
  • Page 6 S2DG2/S2DGU/S2DGE/S2DGR Connecting Cables ... 2-5 Power Supply Connectors ... 2-5 Secondary Power Connector ... 2-5 Infrared Connector ... 2-5 PW_ON Connector ... 2-6 Reset Connector ... 2-6 Hard Drive LED ... 2-6 Keylock/Power LED Connector ... 2-6 Speaker Connector ... 2-7 Power Save State Select ...
  • Page 7 Frequently Asked Questions ... 3-4 Returning Merchandise for Service ... 3-7 Chapter 4: AMIBIOS Introduction ... 4-1 BIOS Features ... 4-2 BIOS Configuration Summary Screen ... 4-3 AMIBIOS Setup ... 4-3 Chapter 5: Running Setup Setup ... 5-1 5-1-1 Standard CMOS Setup ... 5-1 5-1-2 Advanced CMOS Setup ...

  • Page 8: Jumper Quick Reference

    W O L W a k e - O n - L A N * SCSI jumpers and connectors do not apply to the S2DGE. ** S2DG2: Jumping JA5 terminates SCSI connector JA1. Jumping JA6 terminates SCSI connector JA3. Jumping JA7 terminates SCSI connector JA2.

  • Page 9: Front Control Panel Headers

    Front Control Panel Headers P o w e r O n See pages 2-5 through 2-7 for pin definitions. JF2 JF1 H a r d Drive LED IR Con P o w e r L E D K e y b o a r d lock S p e a k e r R e s e t...
  • Page 10 Preface Notes...

  • Page 11: Chapter 1: Introduction

    Graphics Port (AGP), Wake-on-LAN , SDRAM, concurrent PCI and a 33 MB/s Ultra DMA burst data transfer rate. While all of the motherboards are the ATX form factor, the S2DG2, S2DGU and S2DGE have 5 PCI and 2 ISA slots (with one shared). The S2DGR has 4 PCI and 2 ISA slots (with one shared).

  • Page 12: Super S2Dg2 Image

    Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DG2 Figure 1-1. SUPER S2DG2 Motherboard Image...

  • Page 13: Super S2Dg2 Motherboard Layout

    SCSI Termination for JA3 JA7: SCSI Termination for JA2 ——–———————–——–—–——–——–— Note: JA3 is optional. Note: To enable the overheat buzzer, place a jumper on BZ_ON. Figure 1-2. SUPER S2DG2 Motherboard Layout Chapter 1: Introduction 10.65" JP11 UA12 P I I X 4 JBT1...

  • Page 14: Super S2Dgu Image

    Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGU Figure 1-3. SUPER S2DGU Motherboard Image...

  • Page 15: Super S2Dgu Motherboard Layout

    J 3 4 PS/2 KB P S / 2 MOUSE J17, J18 U S B J 1 9 P a r a l l e l Port JP20 PCI 5 PCI 4 J T M J L 2 PCI 3 PCI 2 U 5 8 PCI 1...

  • Page 16: Super S2Dge Image

    Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGE Figure 1-5. SUPER S2DGE Motherboard Image...

  • Page 17: Super S2Dge Motherboard Layout

    J 3 4 PS/2 KB P S / 2 MOUSE J17, J18 U S B J 1 9 P a r a l l e l Port 12" JP20 PCI 5 PCI 4 J T M J L 2 PCI 3 PCI 2 U 5 8 PCI 1...

  • Page 18: Super S2Dgr Image

    Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR SUPER S2DGR Figure 1-7. SUPER S2DGR Motherboard Image...

  • Page 19: Super S2Dgr Motherboard Layout

    J 3 4 PS/2 P S / 2 MOUSE J17, J18 U S B J 1 9 P a r a l l e l Port PCI 4 J T M PCI 3 PCI 2 SBLINK PCI 1 ——–—— Manufacturer Settings —–——— JBT1: 1-2 (default) 2-3 CMOS Clear...

  • Page 20: 440Gx Agp Chipset: System Block Diagram

    Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR C P U C P U Host Bus S D R A M A G P 440GX Port PCI Slots SMBus APIC PIIX4 IDE Ports Power SCSI Management U S B U S B Ports ISA Slots BIOS Figure 1-9.
  • Page 21 Features of the S2DG2, S2DGU, S2DGE and S2DGR Motherboards The following list covers the general features of the S2DG2, S2DGU, S2DGE and S2DGR motherboards. (Note: These boards may run with a single CPU in either slot.) • Dual Pentium II Xeon and dual Pentium III Xeon processors at 100 MHz...
  • Page 22 • SUPER Doctor Utility • SCSI Utility, manual and driver Dimensions • SUPER S2DG2 - ATX (12" x 10.65") • SUPER S2DGU - ATX (12" x 9.65") • SUPER S2DGE - ATX (12" x 9.65") • SUPER S2DGR - ATX (12" x 9.6") Manual ®...

  • Page 23: Chipset Overview

    L2 cache that can run at full CPU speed. PC Health Monitoring This section describes the PC health monitoring features of the SUPER S2DG2/ S2DGU/S2DGE/S2DGR. All have an onboard System Hardware Monitor chip that supports PC health monitoring.
  • Page 24 When the microswitch is closed, it means that the chassis has been opened. The circuitry will then alert the user with a warning message when the system is turned on. This feature is available when the user is running Intel's LANDesk Client Manager and SUPERMICRO's Super Doctor. Manual 1-14...
  • Page 25 The system BIOS is protected by hardware so that no virus can infect the BIOS area. The user can only change the BIOS contents through the flash utility provided by SUPERMICRO. This feature can prevent viruses from infecting the BIOS area and destroying valuable data.

  • Page 26: Acpi/Pc 98 Features

    SUPER S2DG2/S2DGU/S2DGE/S2DGR ACPI/PC 98 Features ACPI stands for Advanced Configuration and Power Interface. The ACPI speci- fication defines a flexible and abstract hardware interface that provides a stan- dard way to integrate power management features throughout a PC system, including hardware, the operating system and application software. This enables the system to automatically turn on and off peripherals such as CD-ROMs, network cards, hard disk drives and printers.

  • Page 27: Power Supply Requirements

    LAN traffic is kept to a minimum and users are not interrupted. The motherboards have a 3-pin header (WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability. Note that Wake-On- LAN can only be used with an ATX 2.01 (or above) compliant power supply.

  • Page 28: Super I/O

    SUPER S2DG2/S2DGU/S2DGE/S2DGR computer from noise. It is recommended that you also install a power surge protector to help avoid problems caused by power surges. Super I/O The disk drive adapter functions of the Super I/O chip include a floppy disk drive...

  • Page 29: Aic 7890 Scsi Controller

    AIC-7890 Ultra2 SCSI Controller Note: If you are using a low voltage differential hard drive, it is recommended that you use an LVD/SE Ultra2 SCSI cable. LVD/SE cables offer increased length and can accommodate up to 15 devices. The SUPER S2DGU has an onboard Adaptec SCSI controller that is 100% compatible with all major operating and hardware platforms.
  • Page 30 SUPER S2DG2/S2DGU/S2DGE/S2DGR 1-10 AIC-7896 Ultra2 Dual Channel SCSI Controller (S2DG2) The SUPER S2DG2 has an onboard Adaptec SCSI controller that is 100% com- patible with all major operating and hardware platforms. PCI 2.1 compliance is assured. The AIC-7896 Ultra2 SCSI chip connects to a 32-bit PCI bus. Two independent Ultra2 LVD SCSI channels provide a per channel data transfer rate of 80 MB/s.

  • Page 31: Chapter 2: Installation

    Static-Sensitive Devices Static-sensitive electrical discharge can damage electronic components. To prevent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from static discharge. Precautions • Use a grounded wrist strap designed to prevent static discharge. •...

  • Page 32: Removing The Pentium Ii/Iii Xeon Processor

    SUPER S2DG2/S2DGU/S2DGE/S2DGR Installing the metal standoffs: Attach the metal standoffs to the back of the motherboard tray. Be sure the location of all the mounting holes for both the motherboard and the chassis match. Make sure the metal standoffs click in or are screwed in tightly.
  • Page 33 Chapter 2: Installation Figure 2-1. Dual Retention Module Mounting Holes When mounting the motherboard to the chassis, note that ATX Standard Extra for you will use three Hole Slot 2 holes specifically for mounting the Slot 2 DRM as well as one Extra for Slot 2 Extra for Slot 2 ATX Standard hole...

  • Page 34: Explanation And Diagram Of Jumper/Connector

    SUPER S2DG2/S2DGU/S2DGE/S2DGR Explanation and Diagram of Jumper/ Connector To modify the operation of the moth- erboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square.

  • Page 35: Mounting The Motherboard In The Chassis

    G r o u n d G r o u n d P W - O K 5 V S B 1 2 V Note: The S2DG2 has two primary power supply connectors located at J32A and J32B. Table 2-3 Secondary Power Connector Number...

  • Page 36: Pw_On Connector

    SUPER S2DG2/S2DGU/S2DGE/S2DGR PW_ON Connector The header for the PW_ON connec- tor is located on pins 9 and 10 of JF2. Momentarily contacting both pins will power on/off the system. The user can also configure this but- ton to function as a suspend button.

  • Page 37: Speaker Connector

    Speaker Connector The header for the speaker connec- tor is located on pins 10 to 13 of JF1. See Table 2-9 for pin definitions. Power Save State Select Refer to Table 2-10 to set JP20. The Power Save State is used when you want the system to remain in the power-off state when you first apply power to the system or when the...

  • Page 38: Atx Serial Ports

    SUPER S2DG2/S2DGU/S2DGE/S2DGR ATX Serial Ports ATX serial port COM1 is located on J20 and serial port COM2 is located on J21. See Table 2-13 for pin definitions. CMOS Clear Refer to Table 2-14 for instructions on how to clear CMOS. For an ATX...

  • Page 39: Chassis Intrusion

    Chassis Intrusion The Chassis Intrusion Detector is located on JL1. See the board lay- outs in Chapter 1 and the PC Health Monitor information on page 1-14 for more information. See Table 2-18 for pin definitions. SLED (SCSI LED) Indicator The SLED connector is used to pro- vide an LED indication of SCSI activ- ity.
  • Page 40 SUPER S2DG2/S2DGU/S2DGE/S2DGR Side View of DIMM Installation into Socket PC100 To Install: Notches Insert vertically and press down until it snaps into place. Pay attention to the two notches. Top View of DIMM Socket Connecting the Parallel Port, Floppy and Hard Disk Drives Use the following information to connect the floppy and hard disk drive cables.

  • Page 41: Parallel Port Connector

    hard disk drives and the SCSI adapter. (Note: Most SCSI hard drives are single-ended SCSI devices.) The SCSI ID is determined either by jumpers or by a switch on the SCSI device. The last internal (and external) SCSI device cabled to the SCSI adapter must be terminated. Table 2-19 Parallel Port Connector J19 Pin Number...

  • Page 42: Scsi Connectors

    SUPER S2DG2/S2DGU/S2DGE/S2DGR SCSI Connectors There are no jumpers to configure the onboard, single-ended SCSI in- terface. Refer to Table 2-22 for the Ultra Wide SCSI pin definitions. Re- fer to Table 2-23 for the 50-pin SCSI pin definitions. Pin Number...

  • Page 43: Ultra2 Lvd/Se Scsi Connector

    Table 2-24 Ultra2 LVD/SE SCSI Connector Connector Contact N u m b e r Signal Names +DB(12) +DB(13) +DB(14) +DB(15) +DB(P1) +DB(0) +DB(1) +DB(2) +DB(3) +DB(4) +DB(5) +DB(6) +DB(7) +DB(P) G R O U N D D I F F S E N S T E R M P W R T E R M P W R R E S E R V E D...

  • Page 44: Agp Port

    SUPER S2DG2/S2DGU/S2DGE/S2DGR Pin # Manual Table 2-25 AGP Port J8 Pin # Spare 1 2 V Vddq3.3 5.0V Spare A D 2 1 5.0V Reserved* A D 1 9 U S B + U S B - G N D...

  • Page 45: Troubleshooting Flowchart

    Troubleshooting Procedures Use the following procedures and chart to troubleshoot your system. If you have followed all the procedures below and still need assistance, refer to the ‘Tech- nical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Before Power On Make sure no short circuits exist between the motherboard and chassis.

  • Page 46: No Power

    SUPER S2DG2/S2DGU/S2DGE/S2DGR No Power Make sure that the default jumper is on and the CPU is correctly set up. Turn the power switch on and off to test the system. If the power is still not on, turn the system power off and change the jumper setting on JP20 from 2-3 to 1-2.

  • Page 47: Losing The System's Setup Configuration

    Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter of the manual or check our web site FAQ (http://www.supermicro.com) before contacting Technical Support. Take note that as a motherboard manufacturer Super Micro does not sell directly to end-users, so it is best to check with your distributor or reseller for troubleshooting services.

  • Page 48: Frequently Asked Questions

    Answer: It is recommended that you do not upgrade your BIOS if you are experiencing no problems with your system. Updated BIOS files are located on our web site at http://www.supermicro.com. Please check our BIOS warning message and the info on how to update it. Also, check the current BIOS revision and make sure it is newer than your BIOS before downloading.
  • Page 49 Question: I have memory problems. What is the correct memory to use and which BIOS setting should I choose? Answer: The correct memory to use for the SUPER S2DG2/S2DGU/S2DGE/ S2DGR is 168-pin DIMMs of 3.3v non-buffered SPD (Serial Present Detection) SDRAM and SDRAM.
  • Page 50 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Question: Do I need the CD that came with your motherboard? Answer: The supplied compact disc has quite a few drivers and programs that will greatly enhance your system. We recommend that you review the CD and install the applications you need.

  • Page 51: Returning Merchandise For Service

    Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA number should be prominently displayed on the outside of the shipping carton and either mailed prepaid or hand-carried.
  • Page 52 Manual SUPER S2DG2/S2DGU/S2DGE/S2DGR Notes...

  • Page 53: Chapter 4: Amibios

    Introduction This chapter describes the AMIBIOS for Intel 440GX Pentium II/III Xeon proces- sors. The AMI ROM BIOS is stored in the Flash EEPROM and can be easily upgraded using a floppy disk-based program. System BIOS The BIOS is the Basic Input Output System used in all IBM ®...

  • Page 54: Bios Features

    BIOS User's Manual American AMIBIOS (c) 1997 American Megatrends, Inc. M e g a Trends 0404981500 Pentium II Motherboard Made in USA R1.0 U P E R BIOS date code Checking NVRAM xxxxx KB OK Hit <DEL> if you want to run SETUP (C) Super Micro Computer, Inc., XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X BIOS Features...

  • Page 55: Bios Configuration Summary Screen

    • Five positive voltage inputs • Two negative voltage inputs • Three fan speed monitor inputs BIOS Configuration Summary Screen AMIBIOS displays a screen that looks similar to the following when the POST routines complete successfully. AMIBIOS System Configuration (C) 1985-1997 American Megatrends Inc., Main Processor : Pentium(tm) II Math Processor...

  • Page 56: Standard Cmos Setup

    BIOS User's Manual Figure 4-1. AMIBIOS Hiflex Setup Utility Screen AMIBIOS Hiflex Setup Utility - Version 1.18 (C)1998 American Megatrends, Inc. All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Power Management Setup PCI / Plug and Play Setup Peripheral Setup Auto-Detect Hard Disks Change User Password...

  • Page 57: Chapter 5 Running Setup

    Chapter 5: Running Setup Chapter 5 Running Setup Optimal and Fail-Safe default settings are in bold text unless otherwise noted. The AMIBIOS Hiflex Setup options described in this section are selected by choosing the appropriate high-level icon from the Standard Setup screen. All displayed icons are described in this section, although the screen display is often all you need to understand how to set the options.

  • Page 58: Boot Sector Virus Protection

    BIOS User's Manual T y p e 1-46 U S E R A U T O C D R O M A R M D Boot Sector Virus Protection The settings for this option are Enabled or Disabled . Entering Drive Parameters You can also enter the hard disk drive parameters.
  • Page 59 5-1-2 Advanced CMOS Setup Quick Boot The Settings are Disabled or Enabled . Set to Enabled to permit AMIBIOS to boot quickly when the computer is powered on. This option replaces the old Above 1 MB Memory Test Advanced Setup option. Setting Description Disabled...
  • Page 60 BIOS User's Manual HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD, ATAPI CD ROM, SCSI, Network or I 0 . The options for the 2nd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE-HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM . The options for the 3rd Boot Device are Disabled, 1st IDE-HDD, 2nd IDE-HDD, 3rd IDE-HDD, 4th IDE- HDD, Floppy, ARMD-FDD, ARMD-HDD or ATAPI CD ROM .
  • Page 61 Chapter 5: Running Setup Keep Current . If selected as Force BIOS, the POST will force the display to be changed to BIOS mode before giving control to any add-on ROM. If no add-on ROM is found, then the current display mode will remain unchanged even if this setup question is selected as Force BIOS.
  • Page 62 BIOS User's Manual CPU Microcode Updation Set this option to Enabled to permit the CPU to be updated on line. The settings for this option are Enabled or Disabled . Internal Cache This option is for enabling or disabling the internal cache memory. The settings for this option are Disabled , Write-thru or WriteBack .

  • Page 63: Advanced Chipset Setup

    Chapter 5: Running Setup adapter cards. The settings are: Disabled , Enabled or Cached . When set to Disabled, the contents of the video ROM are not copied to RAM. When set to Enabled, the contents of the video ROM area from C0000h-C7FFFh are copied (shadowed) from ROM to RAM for faster execution.
  • Page 64 BIOS User's Manual PERR# The settings for this option are Enabled or Disabled . Set to Enabled to enable the PERR# signal on the bus. WSC# Handshake (Write Snoop Complete) This signal is asserted active to indicate that all the snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is complete and that it is safe to send the APIC interrupt message.
  • Page 65 Setting Description None No error checking or error reporting is done. Multibit errors are detected and reported as parity errors. Single-bit errors are corrected by the chipset. Corrected bits of data from memory are not written back to DRAM system memory. Multibit errors are detected and reported as parity Hardware errors.
  • Page 66 BIOS User's Manual SDRAM RAS# to CAS# Delay This option specifies the length of the delay inserted between the RAS and CAS signals of the DRAM system memory access cycle if SDRAM is installed. The settings are Auto (AMIBIOS automatically determines the optimal delay), 2 SCLKs or 3 SCLKs .
  • Page 67 Chapter 5: Running Setup AGP Multi-Trans Timer (AGP Clks) This option sets the AGP multi-trans timer. The settings are in units of AGP clocks: 32 , 64 , 96 , 128 , 160 , 192 , or 224 . AGP Low-Priority Timer This option controls the minimum tenure on the AGP for low priority data transaction for both read and write.

  • Page 68: Power Management Setup

    BIOS User's Manual PIIX4 Delayed Transaction GX is capable of PIIX4 transaction to improve PIIX4 interrupt efficiency. The settings for this option are Enabled or Disabled . Set this option to Enabled to enable delayed transactions for the Intel PIIX4 chip. Type F DMA Buffer Control1 Type F DMA Buffer Control2 These options specify the DMA channel where Type F buffer control is...
  • Page 69 Chapter 5: Running Setup to On/Off , pushing the power button turns the computer on or off. When set to Suspend , pushing the power button places the computer in Suspend mode or Full On power mode. Green PC Monitor Power State This option specifies the power state that the green PC-compliant video monitor enters when AMIBIOS places it in a power savings state after the specified period of display inactivity has expired.
  • Page 70 BIOS User's Manual Suspend Timeout (Minutes) This option specifies the length of a period of system inactivity while in standby state. When this length of time expires, the computer enters suspend power state. The settings are Disabled and 4 Min through 508 Min in 4 minute intervals .

  • Page 71: Pci/Pnp Setup

    Chapter 5: Running Setup 5-1-5 PCI/PnP Setup Plug and Play-Aware OS The settings for this option are No or Yes . Set this option to Yes if the operating system in the computer is aware of and follows the Plug and Play specification.
  • Page 72 BIOS User's Manual This option forces IRQ14 and IRQ15 to a PCI slot on the PCI local bus. This is necessary to support non-compliant ISA IDE controller adapter cards. If an offboard PCI IDE controller adapter card is installed in the computer, you must also set the Offboard PCI IDE Primary IRQ and Offboard PCI IDE Secondary IRQ options.

  • Page 73: Peripheral Setup

    The settings for this option are Enabled or Disabled . When set to Enable this option enables the Adaptec 7895 BIOS on the P6DGS motherboard or the Adaptec 7890 on the P6DGU/P6SGU motherboards. Remote Power On Microsoft's Memphis OS supports this feature which can wake-up the system from SoftOff state through devices (such as an external modem) that are connected to COM1 or COM2.
  • Page 74 CPU1 Fan CPU2 Fan Thermal Control Fan The above features are for PC Health Monitoring. The motherboards with W83781D have seven on-board voltage monitors for the CPU core, CPU I/O, +3.3V, +5V, -5V, +12V, and -12V, and three fan status monitors.

  • Page 75: Auto Detect Hard Disks

    Chapter 5: Running Setup On-Board Parallel Port This option specifies the base I/O port address of the parallel port on the motherboard. The settings are Auto (AMIBIOS automatically determines the correct base I/O port address), Disabled , 378 , 278 or 3BC . Parallel Port Mode This option specifies the parallel port mode.

  • Page 76: Change User Password Change Supervisor Password

    BIOS User's Manual Pri Master Pri Slave Sec Master Sec Slave Select these options to configure the drive named in the option. The setting for Primary Master and Secondary Slave is Auto . The Primary Slave and Secondary Master are Not-Installed . Change User Password Change Supervisor Password The system can be configured so that all users must enter a password every...

  • Page 77: Default Settings

    Default Settings Every option in AMIBIOS Hiflex Setup contains two default settings: a Fail- Safe default, and an Optimal default. 5-5-1 Auto Configuration with Optimal Settings The Optimal default settings provide optimum performance settings for all devices and system features. 5-5-2 Auto Configuration with Fail-Safe Settings The Fail-Safe default settings consist of the safest set of parameters.
  • Page 78 BIOS User's Manual Notes 5-22...

  • Page 79: Appendix A: Bios Error Beep Codes

    Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes & Messages During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process.
  • Page 80 BIOS User’s Manual Beeps Error message Refresh Failure Parity Error Base 64 KB Memory Failure Timer Not Operational Processor Error 8042 - Gate A20 Failure Processor Exception Interrupt Error Display Memory Read/Write Error ROM Checksum Error CMOS Shutdown Register Read/Write Error Refer to the table on page A-3 for solutions to the error beep codes.
  • Page 81 If it beeps... 1, 2 or 3 times 6 times 8 times 9 times 4, 5, 7 or 10 times Appendix A: BIOS Error Beep Codes then ... reseat the DIMM memory. If the system still beeps, replace the memory. reseat the keyboard controller chip.
  • Page 82 BIOS User’s Manual Error Message 8042 Gate -- A20 Error Address Line Short! C: Drive Error C: Drive Failure Cache Memory Bad CH-2 Timer Error CMOS Battery State Low CMOS Checksum Failure CMOS System Option Not Set CMOS Display Type Mismatch CMOS Memory Size Mismatch...
  • Page 83 Error Message CMOS Time and Date Not Set D: Drive Error D: Drive Failure Diskette Boot Failure Display Switch Not Proper DMA Error DMA #1 Error DMA #2 Error FDD Controller Failure HDD Controller Failure INTR #1 Error INTR #2 Error Appendix A: BIOS Error Beep Codes Information Run Standard Setup to set the date and time...
  • Page 84 BIOS User’s Manual Error Message Invalid Boot Diskette Keyboard Is Locked... Unlock It Keyboard Error KB/Interface Error No ROM BASIC Off Board Parity Error On Board Parity Error Parity Error???? Information The BIOS can read the disk in floppy drive A:, but cannot boot the computer.

  • Page 85: Appendix B: Amibios Post Diagnostic Error Messages

    Appendix B: AMIBIOS POST Diagnostics Error Messages AMIBIOS POST Diagnostic Error Messages This section describes the power-on self-tests (POST) port 80 codes for the AMI BIOS. Check PointDescription Code copying to specific areas is done. to INT 19h boot loader next. NMI is Disabled.
  • Page 86 BIOS User’s Manual Check PointDescription The keyboard controller command byte is written. Next, issuing the pin 23 and 24 blocking and unblocking commands. Next, checking if the <End or <Ins> keys were pressed during Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the <End>...

  • Page 87: Appendix B: Amibios Post Diagnostics Error Messages

    Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next. Bus initialization system, static, output devices will be done next, if present. Passing control to the video ROM to perform any required configuration before the video ROM test.
  • Page 88 BIOS User’s Manual Check PointDescription Initializing the bus input, IPL, and general devices next, if present. Displaying bus initialization error messages. The new cursor position has been read and saved. Displaying the Hit <DEL> message next. Preparing the descriptor tables next. The descriptor tables are prepared.
  • Page 89 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next. The memory above 1 MB has been cleared via a soft reset. Saving the memory size next.
  • Page 90 BIOS User’s Manual Check PointDescription The DMA page register test passed. DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
  • Page 91 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription programming been completed. Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next. Returned from WINBIOS Setup and cleared the screen. Performing any necessary programming after WINBIOS Setup next.
  • Page 92 BIOS User’s Manual Check PointDescription Any initialization required after the option ROM test has been completed. printer base address next. Set the timer and printer base addresses. RS-232 base address next. Returned Performing Coprocessor test next. Required initialization before the Coprocessor test is over.
  • Page 93 Appendix B: AMIBIOS POST Diagnostics Error Messages Check PointDescription Returned Next, performing the E000 option ROM had control. Initialization completed. Displaying the system configuration next. Building the multiprocessor table, if necessary. POST next. The system configuration is displayed. Uncompressing the DMI data and initializing DMI. Copying any code to specific areas.
  • Page 94 BIOS User’s Manual If either <Ctrl><Home> was pressed or the system BIOS checksum is bad, the system will next go to checkpoint code E0h. Otherwise, going to checkpoint code D7h. B-10...

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