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IC DESCRIPTION - 7/8 (HD6417034AF112QFP) - 2/4
QQ
3 7 63 1515 0
Pin No.
Pin Name
_____
WAIT
56
___
CS7
PA3
____
WRL
___
57
WR
PA4
_____
WRH
____
58
LBS
PA5
___
RD
59
PA6
_____
BACK
60
PA7
61
VSS
_____
BREQ
62
PA8
________
IRQOUT
___
AH
63
_______
ADTRG
TE
L 13942296513
PA9
DPL
64
TIOCA1
PA10
DPH
65
TIOCB1
PA11
_____
IRQ0
66
TCLKA
DACK0
PA12
_____
IRQ1
67
TCLKB
DREQ0
PA13
_____
IRQ2
68
DACK1
PA14
_____
www
IRQ3
69
DREQ1
PA15
.
70
VCC
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I/O
Wait. Requests the insertion of wait states (TW) into the bus cycle when the external address
I
space is accessed.
O
Chip select 7. Chip select signals for accessing external memory and devices.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Lower write. Indicates write access to the lower eight bits of an external device.
O
Write. Brought low during write access. (Also used as WRL.)
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Upper write. Indicates write access to the upper eight bits of an external device.
O
Upper/lower byte strobe. Upper and lower byte strobe signals. (Also used as WRH and A0.)
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
O
Read. Indicates reading of data from an external device.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
O
Bus request acknowledge.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
–
Ground
I
Bus request. Driven low by an external device to request bus ownership.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Slave interrupt request output.
O
Address hold. Address hold timing signal for a device using a multiplexed address/data bus.
I
A/D trigger input: External trigger input for starting A/D conversion.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Lower data bus parity
I/O
ITU input capture/output compare (channel 1). Input capture or output compare pins.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Upper data bus parity
I/O
ITU input capture/output compare (channel 1). Input capture or output compare pins.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 0.
I
ITU timer clock input. External clock input pins for ITU counters.
O
DMA transfer acknowledge (channel 1). Indicates that DMA transfer is acknowledged.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 1
I
ITU timer clock input. External clock input pins for ITU counters.
DMA transfer request (channel 0). Input pins for external DMA transfer requests.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
I
Interrupt request 2.
O
DMA transfer acknowledge (channels 0 and 1). Indicates that DMA transfer is acknowledged.
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 3.
I
DMA transfer request (channels 0 and 1). Input pins for external DMA transfer requests.
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y
I/O
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
i
–
Power.
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2 9
8
Description
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3
6 7
1 3
1 5
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9 4
2 8
____
0 5
8
2 9
9 4
2 8
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9 9
9 9
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