Akai LCT-4216 Service Manual page 49

42” lcd-tv
Table of Contents

Advertisement

PRELIMINARY DATA SHEET
Comb Filter Video Processor
1. Introduction
The VPC 323xD is a high-quality, single-chip video
front-end, which is targeted for 4:3 and 16:9, 50/60-Hz
and 100/120 Hz TV sets. It can be combined with other
members of the DIGIT3000 IC family (such as
DDP 331x) and/or it can be used with 3rd-party prod-
ucts.
The main features of the VPC 323xD are
– high-performance adaptive 4H comb filter Y/C sepa-
rator with adjustable vertical peaking
– multi-standard color decoder PAL/NTSC/SECAM
including all substandards
– four CVBS, one S-VHS input, one CVBS output
– two RGB/YC
C
component inputs, one Fast Blank
r
b
(FB) input
– integrated high-quality A/D converters and associ-
ated clamp and AGC circuits
– multi-standard sync processing
– linear horizontal scaling (0.25 ... 4), as well as
non-linear horizontal scaling 'Panoramavision'
– PAL+ preprocessing
– line-locked clock, data and sync, or 656-output
interface
CIN
Analog
VIN1
Front-end
VIN2
VIN3
AGC
VIN4
2×ADC
VOUT
Analog
RGB/
Component
YCrCb
Front-End
FB
RGB/
4 x ADC
YCrCb
Fig. 1–1: Block diagram of the VPC 323xD
Micronas
Adaptive
Color
Comb
Decoder
Filter
NTSC
PAL
NTSC
SECAM
PAL
Saturation
Tint
Y/G
Y
Processing
U/B
Cr
Matrix
Contrast
V/R
Cb
Saturation
Brightness
FB
FB
Tint
– peaking, contrast, brightness, color saturation and
tint for RGB/ YC
C
r
– high-quality soft mixer controlled by Fast Blank
– PIP processing for four picture sizes (
1
---
of normal size) with 8-bit resolution
36
– 15 predefined PIP display configurations and expert
mode (fully programmable)
– control interface for external field memory
2
– I
C-bus interface
– one 20.25-MHz crystal, few external components
– 80-pin PQFP package
1.1. System Architecture
Fig.1–1 shows the block diagram of the video proces-
sor
Y
Y
Mixer
2D Scaler
PIP
Panorama
Cr
Cr
Mode
Contrast
Cb
Cb
Brightness
Peaking
2
I
C Bus
Clock
Gen.
20.25 MHz
VPC 323xD
and CVBS/S-VHS
b
1
1
1
, ,
-- -
-- -
----- -
4
9
16
Output
Formatter
ITU-R 656
ITU-R 601
Memory
Control
Sync
+
Clock
Generation
2
I
C Bus
, or
Y OUT
CrCb
OUT
YCOE
FIFO
CNTL
LL Clock
H Sync
V Sync
AVO

Advertisement

Table of Contents
loading

Table of Contents