Advanced Chipset Features Page - ECS EVEm Series User Manual

Advanced Chipset Features Page

This page sets some of the parameters of the mainboard
components including the memory, and the system logic.
CMOS Setup Utility – Copyright ( C ) 1984—2001 Award Software
DRAM Timing By SPD
SDRAM Cycle Length
Bank Interleave
DRAM Clock
DRAM Drive Strength
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
AGP Aperture Size
OnChip USB
OnChip USB 2
USB Keyboard Support
PCI Master 0 WS Write
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
Memory Parity/ECC Check
↑ ↓ → ← : Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: BestPerf. Defaults
This item allows you to enable or disable the
DRAM Timing
By SPD DRAM timing defined by the Serial Presence
Detect electrical.
SDRAM Cycle This field enables you to set the CAS latency
Length time in HCLKs of 2/2 or 3/3. The system
board designer should have set the values in
this field, depending on the DRAM installed.
Do not change the values in this field unless
you change specifications of the installed
DRAM or the installed CPU.
Bank Interleave This item allows you to enable or disable the
Bank Interleave function with 2 banks or 4
banks.
Enables the user to select the DRAM Clock.
DRAM Clock
3: BIOS Setup Utility
Advanced Chipset Features
Disabled
3
Disabled
By Auto
High
Enabled
Enabled
8M
64M
Enabled
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
F7: Optimized Defaults
Item Help
Menu Level
27