5. ENCODER/DECODER, DATA
NDC-842 was developed to further simplify the connection
of the hard disk drive and
it has the same
advantages as T1 NDC10 (MB15546) and is enabled to
connect with a 5 -inch disk drive and floppy disk drive.
VFO data separating function.
Built-in domestic PLL circuit, phase comparator for
N DC-844 and 84 7.
Copes with double density (MFM) and single density
(FM) record system.
Missing data detecting function
Double density (MFM) write compensation
DC5V single power supply.
Operations of NDC842
This active high input clears all the registers including
the mode register and initializes this chip.
(2) Clock Input
1. 4FC (4F-CLOCK)
This is a basic clock used for internal controls and the
write circuit; a half circle of this clock is output as
2. VCK (VCO-CLOCK)
This generates the output clock in the VCO
In Read operations, the clock generated from this clock
is output as the Read-Clock.
(3) Clock Output
1. 2FC (2F-CLOCK)
This outputs a half cycle of 4F-CLOCK.
This outputs the clock generated from VCO-CLOCK in
Read operations, the and the Read-Data is correspon
Except in Read Operations, a negative signal of 2F-
CLOCK is output.
At the switching point with 2F -CLOCK, it is temporarily
set at a high voltage level.
Input the RAW-DATA input and the DRIVE SELECT
signal (RR1, RR2 & DS1) receiver output of the data
is sent from the disk.
When DS1 is at a low voltage level
R R 1 should be
When DS 1 is at a high voltage level, R R2 should be
(4) Read Control Signals
This is an active high gate signal for various Read opera-
2. AEO (AM-ENABLE-D)
Active - should be active when the missing clock data
(address mark) are to be searched
it enables to write the index mark during Read opera
tions and Write operations of the floppy disk mode.
For the latter the AMW signal is to be
(5) Write Control Signals
WGT (WRITE -BATE)
This is an active high gate signal for various Write opera-
Active high - this should be active when data (address
mark) including the missing clock are to be written
For writing the index mark of the floppy, AE1 is also
(6) Read and Other Systems Input and Output
An active low input signal is necessary to recognize the
internal sink field. it is a gate signal for the bit counter
of the raw-data
Therefore, when 00 is used as the synchronized field,
a control signal is necessary which becomes a low
voltage level upon the detection of the 1 F cycle pattern
at M FM and 2 F cycle pattern at FM
DDO, DD1, DD2 (DELAY-DATA-0
The reading edge in all cases is the rise time.
The raw-data selected by the DS1 signal is bas ically
DDO maintains a high voltage level
except at DD1
DD1 corrects the width of raw-data, which inputs
pulse delayed as much as the data w idth.
e.g.: for 5Mbit/s Disk Drive
10- 25ns delay
DD2 is a signal to be input into the built-in phase
comparator. Half of the 4F -CLOCK cycle delay from
DDO is desirable.
3. RSE, RSN
RSL (READ-STROBE-E, N, L)
The reading edge in all cases is the rise time
These are the strobes to be input into the internal data
separator through the same gate.
The reading margin is different between the inner and
the outer of the media for some disk drives, therefore
it is established to be used for error recovering by
inputting off-set data before and after RSN to make
it possible to select each strobe depending on the mode
The desirable delay time is to make a half cycle of
4F-CLOCK the center.
(7) Write and Other Systems Input and Output
WDN, WMD (WRITE-DATA-NRZ, WRITE
When the serial N R2 data corresponding to ZF-CLOCK
from HOC or FDC is input into WDN
the data modified
at MFM or FM are output as WHD
This is valid only when it is MFM
and the Precompe
Select= EXT Precompe = YEX
The capacity of the Write precompensation differs
depending on the drive. When the capacity is not satis-
fied at the internal mode, off-set data PED will be input
before PND and after PLD
3. DWD (DISK -WRITE -DATA)
This is a signal to
input to the disk interface output
drive. it is a serial data output including the Write
compensation and the missing clock