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3) PIN ASSIGNMENTS
3)-1. Host
(1) HDO-HD7 (Host Data Bus)
8-bit bidirectional data bus. Transfer lines of com-
mands, status and Read/Write data.
-
(2) ADRO-ADR1 (Host Address)
-
-
Input pins to select a transfer register and buffer.
ADR1 ADRO
READ(DRD)
WRITE(DWR)
0
0
STATUS
0
0
1
DATA
DATA
1
0
RESULT
1
1
STATUS 1
COMMAND
(3) CS (Chip Select)
An
input
to enable a DAD input pin, DWR input pin,
HDIR input pin, DROE output pin and HDRO output
pin
.
(4) DAD (Data Read)
Receives a strobe signal which puts status, and data of
a Status Register and Output Data Buffer, into 8-bit
bidirectional data bus HDO-HD7
.
(5) DWR (Data Write)
Receives a host signal which sets data and commands
on 8-bit bidirectional data bus HDO-HD7 into an
input data buffer.
(6) HDRO (Host Data Request)
When the Host DMA mode and Host Data Request
Enable are set and CS is at an "H" level, this pin
transmits an "H" level signal.
(7) DROE (Data Request End)
When "H" is set at the fourth bit from LSB of Status
0 Register and CS is at an "H" level, this pin transmits
an "H" level signal.
(8) HDIA (Host Direction)
When "H" is set at the third bit from LSB of Status 0
Register and the Host DMA mode is set at an "H" level
of CS, this pin transmits and "H" level signal.
(9) INTA (Interrupt)
When "H" is set at the second bit from MSB of Status
0 Register, this pin transmits an "H" level signal.
(10) HDEN (Host DMA End")
Transmits an "L" level signal, when Host DMA End
is
set.
(11) RSO (Reset 0)
This schmidt trigger reset pin initializes an internal
circuit and makes an RSTN pin transmit an "L" level
signal.
(12) RS1N (Rest 1")
This schmidt trigger reset pin initializes an internal
circuit and makes an RSTN pin transmit an "L" level
signal.
3)-2. HOC
(1) 00-07 (Data Bus)
8-bit bidirectional data bus. Transfer lines of com-
mands, status and Read/Write data
.
-
23
-
-
M Z
-
5600A
(2) AO-A3 (Address)
Input pins to select a transfer register, buffer and
mode.
AS
A2
A1
AO
INPUT (INN)
OUTPUT (OUTN)
0
0
0
0
0
0
0
0
1
0
0
0
Re..! Switch
0
0
1
I»dA M ode Set
0
1
0
Read Hoat Data
Statue 1 Set
0
1
1
Host Data Request Set
1
0
0
HDC Data Request Set
1
0
1
Ho~t
DMA Eod Reset
1
1
0
HDC Data Set
1
1
1
Status 0 Set
0
0
0
Abort
(3) IOGN (10 Enable*)
An input pin to enable INN and OUTN input pins.
(4) INN (Input*)
Receives a strobe signal which transmits data of the
Switch and Input Data Buffer to 8-bit bidirectional
data bus
00-07.
(5) OUTN (Output*)
Receives a strobe signal which sets data and status on
8-bit bidirectional data bus 00-07 into an Output
Data Buffer and Status Register. This pin also sets a
mode and aborts.
(6) CEXN (Channel 0 Execution*)
Receives a strobe signal which transacts data between a
Data Buffer and 8-bit bidirectional data bus 00-07.
This pin also transmits an "H" or "L" signal from
IORN and IOWN pins
.
(7) PSON (Phase 0*)
An input pin to enable a CEXN pin.
(8) COlA (HOC Direction)
Designates a direction of data transfer. Used together
with the CEXN and PSON pins
.
CDIR "H" Output Data Buffer Data Bus 00-07
CDIR "L" Input Data Buffer Data Bus 00-07
(9) lOAN (10 Read*)
Transmits an "L" level signal, when COlA is "H" and
Channel 0 Execution FF is set. Transmits an "H" level
signal, when CDIR is "L". lOAN is in a high impedance
("Z"), when Channel 0 Execution F F is reset.
(10) IOWN (10 Write*)
Transmits an "L" level signal, when COl R is "L" and
Channel 0 Execution F F is set. Transmits an "H" level
signal, when COlA is "H". IOWN is in a high impedance
("Z"), when Channel 0 Execution F F is set.
(11) DEM (DMA End Mark)
An input pin to enable Host DMA End
.
(12) COM I (Command Interrupt)
Transmits an "H" level signal, when Input Data Buffer
receives a command from 8-bit bidirectional data bus
HDO-HD7
.
(13) CK4F (4 Frequency Clock)
This 10 MHZ-clock input pin is used to complement a
width of a Bus Direction signal.
(14) RSTN (Reset*)
Transmits an "L" level signal by receiving a reset signal
from RSO and RS1.
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