Chapter 4: Timing Specifications; Cpu Hypertransport™ Bus Timing; Hypertransport™ Reference Clock Timing Parameters; Pci Express® Differential Clock Ac Specifications - AMD RS690M Technical Reference Manual

4.1 CPU HyperTransport™ Bus Timing
For HyperTransport bus timing information, please refer to CPU specifications.
4.2 HyperTransport™ Reference Clock Timing Parameters

Table 4-1 HTREFCLK Pad (66.66MHz) Timing Parameters

Symbol Parameter
TIP REFCLK Period
FIP REFCLK Frequency
TIH REFCLK High Time
TIL REFCLK Low Time
TIR REFCLK Rise Time
TIF REFCLK Fall Time
TIJCC REFCLK Cycle-to-Cycle Jitter Requirement
REFCLK Long Term Jitter Requirement
TIJLT
(1µs after scope trigger)
®
4.3 PCI Express Differential Clock AC Specifications
Table 4-2 PCI Express
Parameter
Absolute Minimum Differential Clock Period
Rise Time
Fall time
Rise/Fall Matching
Cycle-to-Cycle Jitter
Duty Cycle
4.4

Side-port Memory Timing (RS690T Only)

The RS690T's side-port memory DDR2 interface complies with all the timing requirements given in the JESD79-2B
specification. Please refer to the JEDEC standard for any timing details.
4.4.1

Read Cycle DQ/DQS Delay

During a memory read cycle, there is a DLL inside the RS690T that can delay each DQS signal with respect to its byte of
the DQ valid window. This delay ensures adequate setup and hold time to capture the memory data. This DLL delay is
programmable through the following registers:
MCA_DLL_SLAVE_RD_0. MCA_DLL_ADJ_DQSR_0 <NBMCIND : 0xE0[7:0]>
MCA_DLL_SLAVE_RD_1. MCA_DLL_ADJ_DQSR_1 <NBMCIND : 0xE1[7:0]>
© 2008 Advanced Micro Devices, Inc.
Proprietary
®
Differential Clock (GFX_CLK, SB_CLK) AC Characteristics
Minimum
9.872
Timing Specifications
Min Typ Max
– 15 –
– 66.66 –
2 – –
2 – –
– – 1.5
– – 1.5
– – 300
– – 1
Maximum
–
175 700
175 700
– 20
– 125
45 55
Chapter 4
Unit Comment
Time intervals measured at 50%
ns
VDDCK threshold point
FIP is the reciprocal of TIP.
MHz
ns –
ns –
ns –
ns –
ps –
ns –
Unit
ns
ps
ps
%
ps
%
41978 AMD RS690M Databook 3.06
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