Cpu Hypertransport™ Interface; Ddr2 Side-Port Memory Interface (Rs690T Only); Table 3-1 Cpu Hypertransport™ Interface; Table 3-2 Ddr2 Side-Port Memory Interface (Rs690T Only) - AMD RS690M Technical Reference Manual

3.3 CPU HyperTransport
Table 3-1 CPU HyperTransport™ Interface
Pin Name
HT_RXCAD[15:0]P,
HT_RXCAD[15:0]N
HT_RXCLK[1:0]P,
HT_RXCLK[1:0]N
HT_RXCTLP,
HT_RXCTLN
HT_TXCAD[15:0]P,
HT_TXCAD[15:0]N
HT_TXCLK[1:0]P,
HT_TXCLK[1:0]N
HT_TXCTLP,
HT_TXCTLN
HT_RXCALN
HT_RXCALP
HT_TXCALP
HT_TXCALN
3.4

DDR2 Side-port Memory Interface (RS690T only)

Table 3-2 DDR2 Side-port Memory Interface (RS690T Only)

Pin Name
MEM_A[13:0]
MEM_BA[2:0]
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CKE
MEM_CKP
MEM_CKN
MEM_CS#
MEM_ODT
MEM_DQ[15:0]
MEM_DM[1:0]
MEM_DQS[1:0]P
MEM_DQS[1:0]N
MEM_COMPP,
MEM_COMPN
MEM_VREF
41978 AMD RS690M Databook 3.06
3-8
Interface
™
Power Ground
Type
Domain Domain
I VDDHT VSS
I VDDHT VSS
I VDDHT VSS
O VDDHT VSS
O VDDHT VSS
O VDDHT VSS
Other VDDHT VSS
Other VDDHT VSS
Other VDDHT VSS
Other VDDHT VSS
Power Ground
Type
Domain Domain
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
O VDD_MEM VSS
I/O VDD_MEM VSS
I/O VDD_MEM VSS
I/O VDD_MEM VSS
I/O VDD_MEM VSS
Other VDD_MEM VSS
Other – VSS
Functional Description
Receiver Command, Address, and Data Differential Pairs
Receiver Clock Signal Differential Pair. Forwarded clock signal. Each byte of
RXCAD uses a different clock signal. Data is transferred on each clock edge.
Receiver Control Differential Pair. For distinguishing control packets from data
packets.
Transmitter Command, Address, and Data Differential Pairs
Transmitter Clock Signal Differential Pair. Each byte of TXCAD uses a different
clock signal. Data is transferred on each clock edge.
Transmitter Control Differential Pair. Forwarded clock signal. For
distinguishing control packets from data packets.
Receiver Calibration Resistor to VDD_HT power rail.
Receiver Calibration Resistor to Ground
Transmitter Calibration Resistor to HTTX_CALN
Transmitter Calibration Resistor to HTTX_CALP
Integrated
Termination Functional Description
Memory Address Bus. Provides the multiplexed row and column
None
addresses to the memories.
None Memory Bank Address
None Row Address Strobe
None Column Address Strobe
None Write Enable Strobe
None Clock Enable
None Memory Differential Positive Clock
None Memory Differential Negative Clock
None Chip Select
None On-die Termination
None Memory Data Bus. Supports SSTL2 and SSTL3.
None Data masks for each byte during memory write cycles
Memory Data Strobes. These are bi-directional data strobes for
None
latching read/write data.
None Do not connect.
Memory interface compensation pins for N and P channel
devices. Connect through resistors to VDD_MEM and ground
None
respectively (refer to the reference schematics for the proper
resistor values).
Reference voltage. It supplies the threshold value for
None distinguishing between "1" and "0" on a memory signal. Typical
value is 0.5*VDD_MEM.
CPU HyperTransport™ Interface
© 2008 Advanced Micro Devices, Inc.
Proprietary