Sony HCD-VM330AV Service Manual page 57

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• VIDEO BOARD IC502 M30622MGA-A58FP (VIDEO CD CONTROLLER)
Pin No. Pin Name
1 SENSE
2 SENSE CLK
3 RESOLUTION
4 CROMA LEVEL
5 DSP CLK
6 TSENS
7 REMOTE IN
8 BYTE
9 CNVSS
10 DSP MUTING
11 CTRL1
12 XRESET
13 XOUT
14 VSS
15 XIN
16 VCC
17 NMI
18 SCOR
19 DSENS
TE
L 13942296513
20 CL680 HINT
21 H.SYNC IN
22 BGP
23 —
24 PWM3
25 —
26 PWM2
27 —
28 PWM1
29 I2C.CLK
30 I2C.DATA
31 DATA1O
32 DATA1I
33 CLK1
34 RTS1
35 DATAO
36 DATAI
37 CLK1
38 P.ON
39 BUS XRDY
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40 BUS
41 BUS XHOLD
42, 43 BUS .
44
OSD.LANGUAGE
45 VSYNC
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I/O
I
Internal status (SENSE) signal input from the CXD3068Q (IC101)
O
Sense serial data reading clock signal output to the CXD3068Q (IC101)
O
Serial data output to the Y amplifier (IC303)
O Serial data latch pulse output to the C amplifier (IC302)
O
Serial data transfer clock signal output to the CXD3068Q (IC101)
I
Disc tray status detection signal input terminal Not used (open)
I
Remote control signal input terminal Not used (open)
External data bus line byte selection signal input terminal
I
"L": 16 bit, "H": 8 bit (fixed at "L")
— Ground terminal Not used
O
Muting on/off control signal output to the CXD3068Q (IC101) "H": muting on
Clock selection signal output to the CXD3068Q (IC101)
O
"L": 16.9344 MHz (double speed), "H": 33.8688 MHz
I
Reset signal input from the system controller (IC801) "L": reset
O
Main system clock output terminal (10 MHz)
—
Ground terminal
I Main system clock input terminal (10 MHz)
—
Power supply terminal (+5V)
I
Non-maskable interrupt input terminal (fixed at "H" in this set)
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
I Disc status detection signal input terminal Not used (open)
I
Interrupt request signal input from the CL680T (IC505)
I
Horizontal synchronized signal input from the CL680T (IC505)
O
BGP signal output to the C amplifier (IC302)
— Not used (open)
O
RFDC PWM signal output to the CXA2581N (IC103)
—
Not used (open)
O
PWM signal output to the CXA2581N (IC103)
— Not used (open)
O
Focus servo drive PWM signal output to the CXA2581N (IC103)
Communication data reading clock signal input or transfer clock signal output with the display
I/O
controller (IC701) and system controller (IC801)
I/O
Communication data bus with the display controller (IC701) and system controller (IC801)
O
Serial data output terminal Not used
I Serial data input terminal Not used
O
Serial data transfer clock signal output terminal Not used
I
Reset signal input terminal Not used
O
Serial data output to the CL680T (IC505) and D/A converter (IC509)
I
Serial data input from the CL680T (IC505)
O Serial data transfer clock signal output to the CL680T (IC505) and D/A converter (IC509)
O
Power on/off control signal output terminal Not used (open)
I
Ready signal input terminal Not used (fixed at "H")
O
Not used (open)
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y
I Hold signal input terminal Not used (fixed at "H")
i O
Not used (open)
I
Destination setting terminal "L": chinese, "H": others (fixed at "H" in this set)
I
Vertical synchronized signal input from theCL680T (IC505) "L" active
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Description
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