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8. CIRCUIT DIAGRAM
12
11
L
K
BASE BAND PROCESSOR
J
I
H
G
F
PCB Version
D2 D3
Version
L
L
L
H
1.0
H
L
1.1
H
H
1.2
E
Boot Mode
Large Block : R109 -> NA, R103 -> 1K
Small Block : R109 -> 10K, R103 -> NA
D
UART
C
VBAT
UT100
3G
2.5G
1
GND
GND
2
RX
RX
UART_RX
3
TX
TX
UART_TX
4
VCHAR
NC1
5
ON_SW
ON_SW
RPWRON
6
VBAT
VBAT
7
PWR
NC2
8
URXD
NC3
USB_DM
9
UTXD
NC4
USB_DP
10
DSR
DSR
11
RTS
12
CTS
B
OJ101
OJ100
A
12
11
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
10
9
8
1V35_CORE
1V8_SD
VBAT
W18
BAT_ID
M_0
V17
RF_TEMP
M_1
Y19
R105
M_2
390K
Y18
M_3
W17
(1%)
M_4
AA18
M_5
Y17
M_6
W16
M_7
AA17
M_8
Y16
M_9
U15
R111
M_10
100K
(1%)
K16
PA_LEVEL
PAOUT11
M12
PAOUT12
N15
I
BB_I
M15
IX
BB_IX
M16
Q
BB_Q
K15
QX
BB_QX
E13
TXON_PA
T_OUT0
B14
FE2
T_OUT1
F11
PA_BAND
T_OUT2
A15
FE1
T_OUT3
E11
DBB_INT
T_OUT4
F12
LED_CNT
T_OUT5
B13
PA_MODE
T_OUT6
TOUT100
C11
T_OUT7
E12
LCD_BACKLIGHT_EN
T_OUT8
C12
DSR
T_OUT9
B12
T_OUT10
B15
BT_LDO_EN
T_IN0
C13
_CHG_EN
T_IN1
D17
RF_EN
RF_STR0
D18
RF_STR1
E15
RF_DA
RF_DATA
B17
RF_CLK
RF_CLK
C18
AFC
W12
RPWRON
CLKOUT0
U12
26MHZ_MCLK
F26M
H15
SWIF_TXRX
H16
SIM_IO
CC_IO
2V62_VIO
K18
SIM_CLK
CC_CLK
K17
SIM_RST
CC_RST
E10
MMC_CMD
MMCI1_CMD
A12
MMC_CLK
MMCI1_CLK
B11
MMC_D[0]
MMCI1_DAT0
C9
R113
R114
MMC_D[1]
MMCI1_DAT1
10k
DNI
F10
MMC_D[2]
MMCI1_DAT2
A14
MMC_D[3]
MMCI1_DAT3
C
D3
MMCI2_CMD
D2
MMCI2_DAT0
F6
VIB_EN
MMCI2_CLK
R115
R116
W11
FWP
DNI
10K
TP100
F2
USB_OEN
IRDA_TX
G2
FLIP
IRDA_RX
2V62_VIO2V62_VIO
A18
TDO
TDO
B18
TDI
TDI
C15
TMS
TMS
C16
TCK
TCK
F13
R103
R112
TRSTN
TRST_N
1K
1K
F16
RTCK
RTCK
E14
TRIG_IN
TRIG_IN
B16
MON1
C10
MON2
AA7
TRACESYNC
TRACESYNC
U11
R110
R109
TRACECLK
TRACECLK
Y9
10K
DNI
PIPESTAT2
PIPESTAT2
T10
PIPESTAT1
PIPESTAT1
Y8
PIPESTAT0
PIPESTAT0
VBUS_USB
KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW3
KEY_ROW4
KEY_ROW5
KEY_COL4
KEY_COL0
KEY_COL1
KEY_COL2
KEY_COL3
10
9
8
7
6
5
1V8_SD
2V62_VIO
2V9_VMME
2V11_RTC
2V5_VAUDB
2V9_SIM
1V35_VPLL
2V5_VAUDA
ADD[0:26]
U8
ADD[0]
MEM_A0
W4
ADD[1]
MEM_A1
T8
ADD[2]
MEM_A2
U6
ADD[3]
MEM_A3
W5
MEM_A4
ADD[4]
AA4
ADD[5]
MEM_A5
T7
ADD[6]
MEM_A6
U7
ADD[7]
MEM_A7
Y5
ADD[8]
MEM_A8
AA5
MEM_A9
ADD[9]
W6
ADD[10]
MEM_A10
T9
ADD[11]
MEM_A11
W7
ADD[12]
MEM_A12
Y6
ADD[13]
MEM_A13
U9
MEM_A14
ADD[14]
W9
ADD[15]
MEM_A15
V1
ADD[16]
MEM_A16
N5
ADD[17]
MEM_A17
U2
ADD[18]
MEM_A18
W2
MEM_A19
ADD[19]
R5
ADD[20]
MEM_A20
T1
ADD[21]
MEM_A21
R4
ADD[22]
MEM_A22
T2
ADD[23]
MEM_A23
P5
MEM_A24
ADD[24]
T3
ADD[25]
MEM_A25
T4
ADD[26]
MEM_A26
M2
MEM_AD0
DATA[0]
L3
MEM_AD1
DATA[1]
J3
DATA[2]
MEM_AD2
L5
MEM_AD3
DATA[3]
M3
MEM_AD4
DATA[4]
N1
MEM_AD5
DATA[5]
P2
MEM_AD6
DATA[6]
N2
DATA[7]
MEM_AD7
J4
MEM_AD8
DATA[8]
K4
MEM_AD9
DATA[9]
U101
K5
MEM_AD10
DATA[10]
L4
MEM_AD11
DATA[11]
R1
DATA[12]
PMB8877
MEM_AD12
M5
MEM_AD13
DATA[13]
M4
MEM_AD14
DATA[14]
P4
MEM_AD15
DATA[15]
R2
MEM_CS0_N
_NAND_CS
P3
MEM_CS1_N
_RAM_CS
N3
TP103
MEM_CS2_N
N4
MEM_CS3_N
U3
MEM_CSA0_N
ADD[27]
U4
ADD[28]
MEM_CSA1_N
T6
MEM_CSA2_N
ADD[29]
T5
MEM_CSA3_N
ADD[30]
T11
FCDP_RBN
FCDP
K2
MEM_WAITN
M1
MEM_ADVN
L1
MEM_RDN
_RD
R3
MEM_WRN
_WR
W3
MEM_BFCLKO1
Y3
MEM_BFCLKO2
SDCLKI
Y2
MEM_SDCLKO
SDCLKO
AA2
MEM_BC0_N
_BC0
V3
MEM_BC1_N
_BC1
U5
MEM_BC2_N
LDQS
Y4
MEM_BC3_N
UDQS
Y7
MEM_RAS_N
_RAS
W8
MEM_CAS_N
_CAS
U10
MEM_CKE
CKE
AA16
32.768KHZ
F32K
AA15
X1002
1
OSC32K
W14
RESET_N
_RESET
H18
C135
C121
RSTOUT_N
Y14
22P
22P
RTC_OUT
RTC_OUT
R16
C116
220N
VREFP
VREFN
R15
IREF
J18
SPCU_RQ_IN0
R106
J19
22K
SPCU_RQ_IN1
H17
(1%)
SPCU_RC_OUT0
G18
SPCU_RQ_IN2
TP102
TP105
TP107
C138
0.1U
2V85_CAM
7
6
5
- 117 -
4
3
2
1
1G NAND(Large Block x16bit) +512M DDR SDRAM
ADD[16:28]
ADD[0:15]
x
TP101
C7
ADD[16]
A0
ADD[0]
B3
C8
ADD[17]
DQ0
A1
ADD[1]
C4
C9
ADD[18]
DQ1
A2
ADD[2]
C3
B8
ADD[19]
DQ2
A3
ADD[3]
ADD[20]
D4
M9
DQ3
A4
ADD[4]
D3
L9
ADD[21]
DQ4
A5
ADD[5]
E4
K9
ADD[22]
DQ5
A6
ADD[6]
E3
J9
ADD[23]
DQ6
A7
ADD[7]
F4
H7
ADD[24]
1V8_SD
DQ7
A8
ADD[8]
ADD[25]
J4
H8
DQ8
A9
ADD[9]
K3
D9
ADD[26]
DQ9
A10
ADD[10]
K4
H9
ADD[27]
DQ10
A11
1V8_SD
ADD[11]
L3
G7
ADD[28]
DQ11
A12
ADD[12]
L4
DQ12
ADD[13]
M3
DQ13
ADD[14]
M4
B4
DQ14
VDD1
ADD[15]
N3
G9
DQ15
VDD2
H2
VDD3
M2
VDD4
E9
_RAM_CS
_CS
U100
D2
VDDQ1
H4
F2
SDCLKO
CLK
VDDQ2
G8
K2
CKE
CKE
VDDQ3
F8
K5E1H12ACB-A075
_WR
_WED
D7
ADD[29]
BA0
D8
C2
ADD[30]
BA1
EUSY0335806
VSS1
E7
F9
_RAS
_RAS
VSS2
F7
G2
_CAS
_CAS
VSS3
G3
N4
_BC0
LDQM
VSS4
H3
_BC1
UDQM
E2
VSSQ1
1V8_SD
J2
VSSQ2
J5
L2
DATA[0]
IO0
VSSQ3
L5
DATA[1]
IO1
DATA[2]
J6
IO2
DATA[3]
L6
B6
IO3
VCC1
DATA[4]
J7
N7
IO4
VCC2
L7
DATA[5]
IO5
J8
N6
DATA[6]
IO6
VCCQ
DATA[7]
L8
IO7
DATA[8]
K5
IO8
DATA[9]
M5
B5
IO9
VSS5
K6
N5
DATA[10]
IO10
VSS6
M6
N8
DATA[11]
IO11
VSS7
DATA[12]
K7
IO12
DATA[13]
M7
IO13
DATA[14]
K8
F3
IO14
LDQS
LDQS
M8
J3
DATA[15]
IO15
UDQS
UDQS
1V8_SD
R104
_NAND_CS
3.3K
SDCLKI
ADD[16]
R108
ADD[17]
10K
TP104
_RD
FCDP
TP106
_WR
ON BOARD ARM9 JTAG & ETM INTERFACE
2V62_VIO
1V8_SD
CN100
G1
G2
1
30
2
29
TRACECLK
3
28
TRACEPKT7
4
27
TRSTN
TRACEPKT6
5
26
TDI
TRACEPKT5
6
25
TMS
TRACEPKT4
7
24
TCK
TRACEPKT3
8
23
RTCK
TRACEPKT2
9
22
TDO
TRACEPKT1
10
21
EXTRSTN
TRACEPKT0
11
20
TRIG_IN
PIPESTAT2
12
19
PIPESTAT1
13
18
PIPESTAT0
14
17
TRACESYNC
15
16
G3
G4
AXT430124
ENBY0029001
4
3
2
1
L
K
J
I
H
G
F
E
D
C
B
A
LGE Internal Use Only
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