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3. Technical Brief

3.6. Memory

1Gbit Flash & 512Mbit DDRAM employed on GD310 with 8 & 16 bit parallel data bus thru ADD(0) ~
ADD(26). The 1Gbit Nand Flash memory with DDRAM stacked device family offers multiple
high-performance solutions.
ADD[0:15]
_RAM_CS
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
_NAND_CS
SDCLKI
ADD[16]
ADD[17]
_RD
FCDP
_WR
LGE Internal Use Only
ADD[0]
B3
DQ0
ADD[1]
C4
DQ1
ADD[2]
C3
DQ2
ADD[3]
D4
DQ3
ADD[4]
D3
DQ4
ADD[5]
E4
DQ5
ADD[6]
E3
DQ6
ADD[7]
F4
DQ7
ADD[8]
J4
DQ8
ADD[9]
K3
DQ9
ADD[10]
K4
DQ10
ADD[11]
L3
DQ11
ADD[12]
L4
DQ12
ADD[13]
M3
DQ13
ADD[14]
M4
DQ14
ADD[15]
N3
DQ15
E9
_CS
H4
SDCLKO
CLK
G8
CKE
CKE
F8
K5E1H12ACB-A075
_WR
_WED
D7
ADD[29]
BA0
D8
ADD[30]
BA1
EUSY0335806
E7
_RAS
_RAS
F7
_CAS
_CAS
G3
_BC0
LDQM
H3
_BC1
UDQM
J5
IO0
L5
IO1
J6
IO2
L6
IO3
J7
IO4
L7
IO5
J8
IO6
L8
IO7
K5
IO8
M5
IO9
K6
IO10
M6
IO11
K7
IO12
M7
IO13
K8
IO14
M8
IO15
TP104
TP106
Figure 10. Flash memory & DDR RAM MCP circuit diagram
x
TP101
C7
A0
C8
A1
C9
A2
B8
A3
M9
A4
L9
A5
K9
A6
J9
A7
H7
A8
H8
A9
D9
A10
H9
A11
G7
A12
B4
VDD1
G9
VDD2
H2
VDD3
M2
VDD4
D2
U100
VDDQ1
F2
VDDQ2
K2
VDDQ3
C2
VSS1
F9
VSS2
G2
VSS3
N4
VSS4
E2
VSSQ1
J2
VSSQ2
L2
VSSQ3
B6
VCC1
N7
VCC2
N6
VCCQ
B5
VSS5
N5
VSS6
N8
VSS7
F3
LDQS
J3
UDQS
1V8_SD
R104
3.3K
R108
10K
- 38 -
Copyright © 2009 LG Electronics. Inc. All right reserved.
ADD[16:28]
ADD[16]
ADD[17]
ADD[18]
ADD[19]
ADD[20]
ADD[21]
ADD[22]
ADD[23]
1V8_SD
ADD[24]
ADD[25]
ADD[26]
ADD[27]
1V8_SD
ADD[28]
1V8_SD
LDQS
UDQS
Only for training and service purposes

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