Only For Training And Service Purposes - LG GD310 Service Manual

Table of Contents

3. Technical Brief

3.2.1. General Description

S-GOLD3

is a GSM/EDGE single chip mixed signal Baseband IC containing all analog and digital

functionality of a cellular radio. Additionally S-GOLD3

software MIDI, MP3 sound. It is designed as a single chip solution, integrating the digital and mixed

signal portions of the base band in 0.09um, 1.2V technology.

The chip will fully support the FR, EFR, HR and AMR-NB vocoding.

S-GOLD3

support multi-slot operation modes HSCSD (up to class 10), GPRS for high speed data

application (up to class 12) and EGPRS (up to class 12) without additional external hardware.

3.2.2. Block Description

Processing core

ARM926EJ-S 32 bit processor core for controller functions. The ARM926EJ-S includes an MMU, and

the Jazelle Java extension for Java acceleration.

- TEAKLite DSP core

ARM-Memory

- 32k Byte Boot ROM on the AHB

- 96k Byte SRAM on the AHB, flexibly usable as program or data RAM

- 16k Byte Cache for Program (internal)

- 8k Byte tightly coupled memory for Program(internal)

- 8k Byte Cache for Data(internal)

- 8k Byte tightly coupled memory for Data(internal)

DSP-Memory

- 104K x 16bit Program ROM

- 8k x 16bit Program RAM

- 60k x 16bit Data ROM

- 37k x 16bit Data RAM

- Incremental Redundancy(IR) Memory of 35904 words of 16bit

Shared Memory Block

1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.

Controller Bus system

The processor cores and their peripherals are connected by powerful buses.

Multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal

and external memories and with the peripheral buses.

Clock system

The clock system allows widely independent selection of frequencies for the essential parts of the

S-GOLD3. Thus power consumption and performance can be optimized for each application.

LGE Internal Use Only

Provides multimedia extensions such as camera,

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