Agp Configuration - Compaq Evo D500 Technical Reference Manual

4.3.2 AGP CONFIGURATION

AGP bus operations require the configuration of certain parameters involving system memory
access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device
integrated within the north bridge (GMCH, device 1) component. The AGP function is, from the
PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI
configuration registers (Table 4-6). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the
GMCH. Function 0 registers (listed in Table 3-4) include functions that affect basic
control (GART) of the AGP.
Table 4-6. PCI/AGP Bridge Configuration Registers (MCH, Function 1)
PCI/AGP Bridge Function Configuration Registers (GMCH, Function 1)
PCI
Config.
Addr. Register
00, 01h Vendor ID
02, 03h Device ID
04, 05h Command
06, 07h Status
08h Revision ID
0A, 0Bh Class Code
0Eh Header Type
18h Primary Bus Number
19h Secondary Bus Number
1Ah Subordinate Bus Number
NOTE:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed
register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI device.
Table 4-6.
PCI
Reset Config.
Value Addr.
8086h 1Bh
1131h 1Ch
0000h 1Dh
0020h 1E, 1Fh
00h 20, 21h
0406h 22, 23h
01h 24, 25h
00h 26, 27h
00h 3Eh
00h 3F-FFh
Compaq Deskpro and Evo Personal Computers
Featuring Intel Celeron and Pentium III Processors
Fifth Edition - March 2002
Technical Reference Guide
Register
Sec. Master Latency Timer
I/O Base Address
I/O Limit Address
Sec. PCI/PCI Status
Memory Base Address
Memory Limit Address
Prefetch Mem. Base Addr.
Prefetch Mem. Limit Addr.
PCI/PCI Bridge Control
Reserved
Reset
Value
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
00h
00h
4-13