Sa7121 (Hdmi: U4203); Sa7121 Block Diagram - Denon AVR-3311CI Service Manual

SA7121 (HDMI : U4203)
res. 1
2
SP
AP 3
4
LLC
V SSD1
5
V DDD1
6
RCV1 7
RCV2 8
MP7 9
MP6 10
MP5 11
SA7121 Block Diagram
handbook, full pagewidth
RESET SDA SCL
Philips Semiconductors
9 to 16
MP7
to
Digital Video Encoder (ConDENC)
MP0
SYMBOL PIN
44
TTX
V 38
SSD3
V 39
DDD3
RESET 40
5, 18, 38
SCL 41
V SSD1,
SDA 42
V SSD2 ,
TTXRQ 43
V SSD3
TTX 44
handbook, full pagewidth
SAA7120
SAA7121
SA
40 42 41 21
2
I C-BUS
INTERFACE
SAA7120
SAA7121
2
I C-bus
control
Y
DATA
ENCODER
MANAGER
CbCr
2
I C-bus
control
I/O
I
I digital ground 3
I digital supply voltage 3
I reset input, active LOW; after reset is applied, all digital I/Os are in input mode;
1, 20, 22,
2
the I C-bus receiver waits for the START condition
6, 17, 39 23, 26, 29
2
I I C-bus serial clock input
res.
V DDD1,
2
I/O I C-bus serial data input/output
V DDD2 ,
O teletext request output, indicating when bit stream is valid
V DDD3
I teletext bit stream input
res. 1
SP 2
33 V SSA2
V SSA1
32
V DDA3
31
30 CVBS
29 res.
V DDA2
28
27 Y
res.
26
V DDA1
25
24 C
res.
23
MBH790
RCV1 TTXRQ
RCV2 XCLK
7 8 43 37 34 35 4
SYNC
CLOCK
clock
and timing
Y
OUTPUT
INTERFACE
C
DESCRIPTION
2
C-bus
control
19 2 3
RTCI SP AP
183
V DDA1,
XTALO LLC
V DDA2 ,
V DDA4
V DDA3
XTALI
25, 28, 36
31
2
I C-bus
control
Preliminary specification
30
D
27
SAA7120; SAA7121
24
A
2
I C-bus
control
32, 33
MBH787
33 V SSA2
V SSA1
32
V
CVBS
Y
C
V SSA1
V SSA2