Sony CDX-C8850 Service Manual page 29

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L 13942296513
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Pin Name I/O
SIN I Serial data input (Fixed at "L" in this set.)
BCK I Clock signal input for serial bit transfer of serial input/output data.
LRCK I Sampling frequency clock signal input of serial input/output data.
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select
XMST I
signal input from system control (IC500). ("L" : master mode, "H" : slave mode)
VDD3 — Digital power supply pin (+3.3 V)
AVSP — PLL system ground
PLLEN I PLL enable signal input (Normally, fixed at "L".)
PLCLK O PLL clock signal output (Not used in this set.)
CKSTP I PLL clock output control signal input from system control (IC500).
AVDP — PLL system power supply pin (+3.3 V)
VSS4 — Digital ground
TD14 – 23 I Test pin (Normally, fixed at "L".)
VDD4 — Digital power supply pin (+3.3 V)
AVSD — Ground (for D-RAM)
SCLI I Not used. (Normally, fixed at "L".)
BIM I Not used. (Normally, fixed at "L".)
SDRAM I Not used. (Normally, fixed at "L".)
AVDD — Power supply pin (+3.3 V) (for D-RAM)
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Pin Description
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2 8 9 9
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