Denon S-102 Service Manual page 56

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W9864G2GH-7 (IC402: 1U-3836)
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PIN DESCRIPTION
PIN NAME
A0−A10
BS0, BS1
DQ0−DQ31
CS
RAS
CAS
WE
DQM0−
DQM3
CLK
CKE
V
CC
V
SS
V
CCQ
V
SSQ
NC
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2 9
8
FUNCTION
Address Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
Bank Select Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Data Input/ Multiplexed pins for data output and input.
Output
Chip Select Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Row Address Command input. When sampled at the rising edge of the
Strobe
clock RAS , CAS and WE define the operation to be
executed.
Column Address
Referred to RAS
Strobe
Write Enable
Referred to RAS
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
Clock Inputs System clock used to sample inputs on the rising edge of
clock.
Clock Enable CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground Ground for input buffers and logic circuit inside DRAM.
Q Q
3 6 7 1 3 1 5
Power (+3.3V) for Separated power from V
I/O buffer
Ground for I/O Separated ground from V
buffer
No Connection No connection
co
.
56
9 4 2 8
DESCRIPTION
0 5 8 2 9 9 4 2 8
, to improve DQ noise immunity.
CC
, to improve DQ noise immunity.
SS
m
S-102
9 9
9 9