Control Signals; Serial Data Lines - Furuno FS-1503 Service Manual

3. Control Signals

There are two ways for the CPU to control the transmitting/receiving circuits. One is, the
CPU directly sends signals to them, and the other is, the CPU sends serial data to each
circuit board and there the data are converted to parallel data that controls each circuit.
The CPU controls TX/RX board and PA/FIL board by sending serial-data from P40:
DATA, and DDS circuit in TX/RX from P90: DDS DATA.
CPU (05P0665)
ST PA/FIL
P47
ST TX/RX
P46
CLK
P41
DATA
P40
U6
HD6475328F10
or
HD6435328F
PLL 3 ENB
P43
PLL 1 ENB
P42
ST SYN
P45
DDS LOAD
P44
DDS CLK
P91
DDS DATA
P90
Serial-data transmission has an advantage of smaller number of control lines than paral-
lel-data transmission. However, the signals T/R, MUTE, EXC ON, PA ON, TX KEYED,
and BK ON are directly sent as parallel data from CPU, because these signals need pre-
cisely matched timing with their object circuits.
Whereas DATA CLK for the serial-data is periodically sent from the CPU, ST (LATCH)
signal is sent to control the circuit (M54972P) when the data are changed by key opera-
tions.
The transmission timing of the serial-data is shown in Figure 2-4 and the functions of the
serial control signals are listed on Table 2-3.
TX/RX (05P0666)
U12
U503 U502
(1Lo) (1Lo)
U501
(DDS)
Figure 2-3 Serial Data Lines
U11
U504
(3Lo)
• U11 (M54972FP)
• U12 (M54972FP)
• U501 (AD7008AP20)
• U502 (MC145170D1)
• U503 (M54972FP)
• U504 (MC145170D1)
2-9
PA/FIL (05P0667)
U7 (M54972P)