Transmission Timing; Block Diagram Of M54972P - Furuno FS-1503 Service Manual

Serial-data
LATCH (ST)
M54972P (8BIT SERIAL INPUT LATCHED DRIVER)
Vcc
4
power
EN
7
Enable input
LATCH
6
Latch input
Sin
2
Serial data input
T
1
clock
M54972P consists of 8 D-flip-flops and 8 latches connected to the outputs of the flip-
flops. Serial-data signals input to the serial-data input (S-in) and clock pulses input to the
clock input (T). Every time the clock changes from L to H, the input signal is taken in the
internal shift register and the data in the shift register shifts successively.
The serial output (S-out) is connected to the serial input (S-in) of the next M54972P,
when more than one M54972P are connected in series to increase bit number.
The data in the shift register output to the parallel output Q1 to Q8, when the latch input
(LATCH) is H, the enable input for output control (EN) is L, and the clock changes from
L to H.
CLK
While data and clock are sent from CPU, changed data is taken in by LATCH signal.
Figure 2-4 Transmission Timing
O1 O2 O3
16 15 14
Q Q Q
LD LD LD
D Q D Q D Q
T T T
3
Figure 2-5 Block Diagram of M54972P
O4 O5 O6 O7
13 12 11 10
Q Q Q Q
LD LD LD LD
D Q D Q D Q D Q
T T T T
2-10
O8
9
P-GND
8
Driver GND
Q
LD
S out
5
D Q
serial output
T