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TAD-M30
3-2. BLOCK DIAGRAM — DIGITAL SECTION —
SELECTOR
IC105
IC108
J101
3
6
COAXIAL
5
A1
Y1
5
2
DIGITAL
OPTICAL
IN
3
6
B1
IN
IC101
S
1
DIGITAL
OPTICAL
OUT
3
OUT
IC102
IC191
1
7
6
2
X191
12.288MHz
65
16
DIR
IC201
7
47
D IN
D OUT
35
IC109
6
2
3
5
BCK
34
1
7
IC107
RST
6
2
3
5
11
RST
LRCK
36
SWDT
40
SWDT
XLAT
1
7
41
XLAT
SCLK
42
SCLK
ERROR
IC110
IC110
30
ERROR
5
6
CLK
SRDT
28
38
SRDT
XO
XI
27
26
X201
24.576MHz
CLOCK
COUNTER
IC112
IC111
3
5
1
CK1
QB1
4
IC111
1
7
2 76 77 78
67 75
SYSTEM CONTROL
IC151(1/2)
— 7 —
DIGITAL SIGNAL PROCESSOR
IC118
SDI0
SDO0
SDI0
57
47
57
SDI1
SDO1
SDI1
AUDIO
56
46
56
I/F
SCKT
SCKR
49
51
SCKR
WST
WSR
51
50
55
MEMORY
49
50
WSR
55
EXTAL
DSP
27
EXTAL
PLL
HOST I/F
27
36
41
35
26
42 43
20
19 21 22 18 17
DIGITAL SIGNAL PROCESSOR
IC119
SDO0
47
SDO1
AUDIO
46
I/F
SDO2
47
71
.
SCKT
69
MD0
WST
8
67 .
MEMORY
MD7
65
PLL
62
DSP
25
14
22
11
.
.
MA0
HOST I/F
20
7
.
MA15
18
5
.
16
3
MCA
80
MRD
77
MWR
78
36
76 75 74
41
35
26
42 43
26
29
30 31
25 27 28 24 23
— 8 —
DATA (FRONT)
DATA (C/S)
DATA (REAR)
S RAM
23
IC120
.
25
13
28
15
A0
MD0
.
.
8
16
31
17
A15
MD7
.
2
21
11
12
A16
24
OE
29
R/W
BCK
LRCK
IC110
9
8
CLK (FRONT)
IC110
11
10
CLK (C/S)
IC110
13
12
CLK (REAR)
MUTE
• R-CH is omitted
• Signal Path
: DIGITAL
: ANALOG
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