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IC118 DSP56009FJ88F (DIGITAL SIGNAL PROCESSOR)/MAIN BOARD
Pin No.
Pin Name
I/O
1
AGND
2
MSC0
3
MSC3
4
MA14
5
MA13
6
AVCC
7
MA12
8
AGND
9
QVCC
10
QGND
11
MA11
12
MA10
13
MA9
14
MA8
15
AGND
16
MA7
17
AVCC
18
MA6
19
MA5
20
MA4
21
AGND
22
MA3
23
MA2
24
MA1
25
MA0
26
SCK
27
EXTAL
28
QVCC
29
QGND
30
PINIT
31
PGND
32
PCAP
33
PVCC
34
SGND
35
MISO
36
RESET
37
MODA
38
MODB
39
MODC
40
SVCC
—
Address buffer Ground
O
Chip select 0 output to SRAM (Not used)
O
Chip select 3 output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
—
Address bus buffer power supply (+5 V)
O
Address data output to SRAM (Not used)
—
Address bus buffer Ground
—
Power supply for internal logic (5 V)
—
Ground for internal logic
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
—
Address bus buffer Ground
O
Address data output to SRAM (Not used)
—
Address bus buffer power supply (+5 V)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
—
Address bus buffer Ground
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
O
Address data output to SRAM (Not used)
I
SPI serial clock signal input from system controller
I
External frequency input (3 MHz)
—
Power supply for internal logic (5 V)
—
Ground for internal logic
I
PLL initialize input (Fixed to "L")
—
Ground for PLL
I
PLL filter input (Connected to 0.01 uF capacitor)
—
Power supply for PLL (+5 V)
—
Ground for serial port
I
Master data input from system controller
I
Reset signal input from system controller
I
Mode select A (Fixed to "H")
I
Mode select B (Fixed to "L")
I
Mode select C (Fixed to "H")
—
Power supply for serial port (+5 V)
Description
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