Sharp UX-B20 Service Manual page 59

2.6.11 Fax Engine Bus Interface
This interface has a bridging function for connecting the external bus
of Fax Engine LSI and the internal bus of ASIC. Due to the system
clock condition, 1WAIT or more must be set to activate Fax Engine.
2.6.12 Interrupt Controller
This controller logs major causes of interruption in the ASIC and sends
interrupt signals according to the interrupt status of the Fax Engine
firmware (allowed or prohibited). The causes can be cleared or stored.
External interrupt to Fax Engine is generated at L active level.
2.6.13 Memory Access Arbiter
This arbiter arbitrates memory access from each buffer. There are 7
access channels. The arbitration is controlled by priority to maintain
the data transfer rate of the data output channel to the head.
After arbitration, this arbiter notifies the SDRAM controller of memory
addresses and access types and then waits until memory access is
completed.
Serial Data I/F
Serial Data
Receiving
Circuit
Input Buffer
384kWord
Enlargement/
Reduction/
Resolution
Conversion Circuit
Print Buffer
512kWord
Spitfire
controller
Serial Control I/F
Spitfire-LSI
Ink Cartridge
(208 Heaters)
Fax Engine
Fax Engine Bus I/F
Interrupt Fax Engine
Controller Bus Interface
Registers
Memory
Access
Arbiter
White Skip indication
Split Printing/
White Skip
Split Printing indication
Measuring Circuit
Carriage Motor Feeder Motor
Control Circuit Control Circuit
Thunderbolt I/F
Serial Control I/F
Thunderbolt
Carrier Feed
Motor Motor
2.6.14 SDRAM Controller
This controller accesses the memory by controlling the read cycle,
write cycle, and AUTO refresh cycle of a 16-bit wide 16Mbit Synchro-
nous DRAM.
A refresh cycle is automatically inserted by distributed refresh exe-
cuted every 15.6µs (maximum), and when initialization sequence is
performed after reset.
2.6.15 Sensor Detection Circuit
For home position sensor input and paper detection sensor input, this
circuit eliminates noises such as chattering. The detection method is
based on multiple sampling (sequential matching). The sampling clock
is 1.008 MHz and detection time in the register setting should be
approximately between 2µs ~ 65 ms, and can be set for the rising
edge and the falling edge individually.
System Clock
32.256MHz
PrinterASIC
Test etc.
Memory
Bus
SDRAM
Controller
Entire
Mechanism
Sequence
Controller
Sensor
Detection
Circuit
Sensors
Fig. 5
5 – 10
UX-B20U/UX-B20C/B25C
Motor table
x16 SDRAM
128kWord
16Mbit
Input Buffer
384kWord
Print Buffer
512kWord