Sharp UX-B20 Service Manual page 57

2.5. Modem block (CX06835)
2.5.1 Integrated Analog Control Resisters for CX06835
The CX06835 IA can be used as a Primary Integrated Analog (PIA) codec or as a Secondary Integrated Analog (SIA) codec, depending on the signal
connection with the SCE Controller ASIC device. In the SCE100 product, both the PIA and the SIA are packaged external to the SCE Controller
device, whereas in the SCE209, the PIA is packaged with the SCE209 Controller and the SIA is external.
The CX06835 IA provides gain, filtering, internal analog switching, and an internally sourced microphone bias output. The IA is controlled by three
control registers and an address register located in internal RAM space which are accessed via the modem interface memory. These registers pro-
vide individual controls for the IA's inputs, outputs, gain settings, and switching.
The registers are located in internal DSP RAM. Each bit of each 8-bit IA control register has exactly the same meaning for the PIA and the SIA. The
LSB of each 16-bit address contents is used to control the PIA. The MSB of each 16-bit address contents is used to control the SIA.
The following table the PIA/SIA control register RAM access code.
Register SBRAMx
IACR1 0
IACR2 0
IACR3 0
IAADD 0
NOTES: *Registers to use when x=1. When x=2, add 10h.
• For changes made to IACR1 to be effective, the host must write to IAADD with a value of 0002h.
• For changes made to IACR2 to be effective, the host must write to IAADD with a value of 0006h.
• For changes made to IACR3 to be effective, the host must write to IAADD with a value of 0007h.
Configuration default values are shown below.
CONFIGURATION
V.17/V.33
V.29
V.27ter
V.21 Ch. 2
V.23/Caller ID
Tone Transmit/Detect
Voice/Audio Codec
Speakerphone
The following signal flow block diagram is for a signal IA and it applies to both PIA and SIA.
BRx Crx
0 0
0 0
0 0
0 0
DEFAULT VALUE
IACR1
1D9Eh
1D9Eh
1D9Eh
1D9Eh
1D9Eh
1D9Eh
0D16h
0D16h
LINE IN ENABLE MIC ENABLE
MICP
MICM
GAIN
LPF
LINEIN
0, 20, 25, 30 dB(MIC IN)
0dB(LINE IN)
LINE OUT ENABLE
LINE OUT
LINE LINE IN
DRIVER SELECT
Mute, 0, -6, -12 dB
SPKRP
SPEAKER
RT
DRIVER
Loop
SPKRM
(1,1)
SPEAKER OUT ENABLE
Fig. 4 PIA/SIA Signal Flow Control
IOx AREXx
0 0
0 0
0 0
0 0
IACR2
0008h
0008h
0008h
0008h
0008h
0008h
0008h
0008h
ADC
0, +4 dB
(1,0)
(1,1)
(0,0)
(0,0)
DAC
(1,0)
(0,1)
0, 6 dB
5 – 8
UX-B20U/UX-B20C/B25C
ADDx PIA Reg* SIA Reg*
D0 0
D4 0
D5 0
CE 0, 1
IACR3
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
SOUT
SIN
1
1
1
0, 1