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Paragraph
Number
6.3.2.2
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.2
6.4.2.1
6.4.2.2
6.5
6.6
6.6.1
6.6.2
6.6.2.1
6.6.2.2
6.6.3
6.6.3.1
6.6.3.2
6.6.3.3
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.8
6.9
6.9.1
6.9.1.1
6.9.1.2
6.9.2
TABLE OF CONTENTS (Continued)
Title
Page
Number
External Cycle Steal Mode ..................................................................... 6-5
Data Transfer Modes ........................................................................................ 6-6
Single-Address Mode ..................................................................................
6-6
Single-Address Read ...............................................................................
6-7
Single-Address Write ...............................................................................
6-9
Dual-Address Mode .....................................................................................
6-12
Dual-Address Read ..................................................................................
6-12
Dual-Address Write ..................................................................................
6-14
Bus Arbitration ...................................................................................................
6-18
DMA Channel Operation .................................................................................
6-18
Channel Initialization and Startup .............................................................
6-18
Data Transfers ...............................................................................................
6-19
Internal Request Transfers ......................................................................
6-19
External Request Transfers .....................................................................
6-19
Channel Termination ...................................................................................
6-20
Channel Termination ...............................................................................
6-20
Interrupt Operation ....................................................................................
6-20
Fast Termination Option ..........................................................................
6-20
Register Description .........................................................................................
6-22
Module Configuration Register (MCR) ......................................................
6-23
Interrupt Register (INTR) ..............................................................................
6-26
Channel Control Register (CCR) ...............................................................
6-26
Channel Status Register (CSR) .................................................................
6-30
Function Code Register (FCR) ...................................................................
6-32
Source Address Register (SAR) ................................................................
6-33
Destination Address Register (DAR) .........................................................
6-33
Byte Transfer Counter Register (BTC) ......................................................
6-34
Data Packing .....................................................................................................
6-35
DMA Channel Initialization Sequence .........................................................
6-36
DMA Channel Configuration ......................................................................
6-36
DMA Channel Operation in Single-Address Mode ............................
6-37
DMA Channel Operation in Dual-Address Mode ...............................
6-37
DMA Channel Example Configuration Code ..........................................
6-38
Section 7
Serial Module
7.1
Module Overview ..............................................................................................
7-2
7.1.1
Serial Communication Channels A and B ...............................................
7-3
7.1.2
Baud Rate Generator Logic ........................................................................
7-3
7.1.3
Internal Channel Control Logic ..................................................................
7-3
7.1.4
Interrupt Control Logic .................................................................................
7-3
xii
MC68340 USER'S MANUAL
MOTOROLA
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