4-3 FREQUENCY SYNTHESIZER (MAIN UNIT)
• VCO
The VCO (Q21, Q22, and D20–D22) generates both the 1st
LO signal and the TX signal. The generated signal is ampli-
fi ed by buffers (Q23 and Q24), and then used as the TX or
RX LO signal.
In receive, the LO signal is applied to the 1st IF mixer (Q150),
through the LO SW (D51) and BPF (L26 and C122).
In transmit, the LO signal is applied to the TX AMP circuits,
through the LO SW (D50).
• FREQUENCY SYNTHESIZER CIRCUITS
IC1
PLL IC
X1
REF.OSC
2ND LO
4-4 VOLTAGE DIAGRAMS
Voltage from the power supply is routed throughout the transceiver, through regulators and switches.
CHASSIS
Q353
VCC
HV
PWR
CTRL
GND
Q354
PWR
PWSW
CTRL
Q354
PON
MAIN UNIT
Q21,Q22
D20-D22
LOOP
BUFF
FIL
PLLO
BUFF
Q25
RF UNIT
CPU3.3V
M5V
REG
5V
M5VS
Q224
Q225
Q363
RVS
T5VS
IC383
1.8V
REG
DC
1.1V
5V
DC
IC384
CPU3.3V
CPU
CPU
3.3V
IC220
• PLL
A portion of the VCO output signal is passed through two buf-
fers (Q23 and Q25), and then fed back to the PLL IC (IC1, pin
16), through the LPF (L20, C21 and C22).
The PLL IC (IC1) phase compares the outputs of the ref-
erence frequency oscillator (TCXO; X1) and VCO, and the
phase difference is output as the charge pump current.
The current is passed though the loop fi lter (R10, R22, C11,
C13, C18 and C24) to be converted into the lock voltage,
which controls the oscillating frequency of VCO.
When the oscillation frequency drifts, its phase changes from
that of the reference frequency, causing a lock voltage change
to compensate for the drift in the VCO oscillating frequency.
Q24
D50,D51
LO
BUFF
SW
BPF
1st LO
1st IF mixer
COMMON circuit
Q221
Q365
REG
R5V
RX circuit
R5
Q222
Q364
T5V
REG
TX circuit
T5
GPS MODULE
NOISE CANSEL IC
4 - 3
TX AMPs
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