Akai LT-32Q5LFH Service Manual page 63

7. VCT 49xyI-C7
The VCT 49xyI-C7 is pin-compatible to VCT 49xyI-C6 and VCT 49xyI-C4.
Problem 45 has been solved. Problem 43 is partly solved: Improved internal clock suppression leads to reduced
noise floor and better video snr. Problems 53 and 54 have not been detected before D2.
VCT 49xyI-C7 includes functionality of DRX396xA-H8.
Table 7–1: Functional problems of VCT 49xyI-C7:
No. Problem
18 Vertical Synchronisa-
tion
26 Picture Frame Blanked
34 Reset after Read
39 Peaking Filter
40 Bandwidth of Antialias
Filter
41 SVM Overflow
42 ADC Initialisation
43 Clock Noise
46 HORPOS changes
color multiplex
47 Preframe Generator
CIRCUIT DESCRIPTIONS
Description
Vertical pull-in after channel
change takes too long
Left side of picture frame is blanked
if HORPOSG<180.
All I2C register with "reset by read"
are not functional (NMSTATUS,
LBDSTATUS, FBLACTIVE,
FBFALL, FBRISE, PFBL/G/R/B).
In case of PKCF=2,3, the dynamic
peaking adaption doesn't work.
Thus the peaking signal is limited
only.
The bandwidth adjustment of the
antialias filter 1-6 is disturbed. This
causes wrong filter settings after
reset and/or after a modification of
TRIM_FILTER1-6
The SVM output signal is not lim-
ited correctly over the full range of
SVLIM.
Wrong initialisation of RGB ADCs
after power-on causes color mis-
match.
Induced harmonics of the system
clock generate visible interference
on weak IF input signals.
When picture is shifted to the right
via HORPOS the color multiplex is
inverted.
The preframe generator cannot
produce full screen background
color.
Comment
hardware redesign D1
workaround:
increase LPFOPOFF
hardware redesign D1
hardware redesign D1
hardware redesign D1
hardware redesign D1
workaround:
<0xb0 0x2f 0x00 0x01>
hardware redesign D1
workaround:
SVLIM = 31
hardware redesign D1
workaround:
<0xb0 0x37 0x00 0xe4>
hardware redesign D1
hardware redesign D1
workaround:
HORPOS+HORWIDTH < 1287
hardware redesign D1
OK
D1
D1
D1
D1
D1
D1
D1
D1
D1