Epson LX-HOO Technical Manual page 130

Pin Signal
P A O - 7
1 - 8
9 - 1 6 PBO - 7
Pco - 7
1 7 - 2 4
25
26
MODE 1, 0
27, 29
28 RESET
x2, xl
32
33
3 4 - 4 1
42 VAref
43
44
45 WR
46 ALE
4 7 - 5 4 PFO -7
5 5 - 6 2
P D O - 7
63
64
Table A-5. APD7810/7811 Port Functions
Direction
In/Out
(MA) register. Output HIGH.
In/Out
register (MB). Output HIGH.
Port C. Eight-bit l/O with output latch. Port/control mode can be
In/Out
set by mode control C (MCC) register. Output HIGH.
In
In Maskable interrupt input of the edge trigger (leading edge). Also
used as the AC input zero cross detecting terminal.
In/Out 781 1: O = LOW and 1 = HIGH
7810 modes set in accordance with external memory (see Table
A-2).
In LOW reset
—
Crystal connection for built-in clock pulse. When clock pulses are
supplied externally, input must be to Xl.
.
Supply voltage, Vss, OV
—
Analog Vss
Eight analog inputs of the A/D converter. AN7 -4 can be used
as the input terminals to detect the leading edge and to set the
test flag upon detection of the trailing edge.
In Reference voltage
—
Analog Vcc
out Read strobe. LOW at the read machine cycle and at reset, HIGH
at other times.
out Write strobe. LOW during the write machine cycle and at reset,
HIGH at other times.
Address latch enable. Latches the lower 8 address bits to access
out
external memory.
Port F
781 1: Port bit-by-bit 1/0 possible by mode F register. In exten-
sion mode, gradual address output assignment is possible in
accordance with the size of external memory. See Table A-3.
78 10: By setting modes O and 1, assignment to the address bus
(AB 15 - 8) can be made in accordance with the size of the
external memory. The remaining terminals can be used as 1/0
ports. See Table A-4.
Port D.
781 1: Port bit-by-bit 1/0 possible.
In extension mode, PD7-O act as the multiplexed address/data
bus (AD7-0).
78 10: Multiplexed address/data bus to access external memory.
—
Supply voltage, Vm, +5V
—
Supply voltage, Vcc, +5V
A-5
Description
REV.-A