Read After Step Timing - NEC FDl165 Product Description

3.6e6
Read After Step
The required time relationship of controller signals during
a READ AFTER STEP operation is shown in Figure 3-14.
HEAD LOAD (HDL) - - , _
1---50 m, IMINI--.j
STEP (STP) ~-----------------
---1
1---
,8
m,lMINI
SIDE SELECT (SSL)
1
-------~'-~I-
..
--1-00-IIS-(-M-IN-)--------
READ DATA (ROT)
---------~Wh~~~~~:ESrnWJw~~~.
WRITE GATE (WGT)
-------..11
---j
Figure 3-14 Read After Step Timing
3-12