Certance LTO-2 Online User's Manual page 32

Theory
Error-correction Code (ECC)
The use of Cyclic Redundancy Checking (CRC), two-level orthogonal Error Correction Coding (ECC)
provides a very low probability of encountering a hard error. During the read process, ECC correc-
tion is performed on the fly without affecting tape streaming.
There are two levels of Error Correction Coding (ECC). These two levels are orthogonal — that is, an
ECC codeword at one level intersects ECC codewords at the other level just once, which means
there will be only one common symbol between them. The two levels are called C1 and C2.
C1 ECC
As data is written to memory from the Data Processing unit, the DMA / ECC interface generates C1
ECC bytes and writes them to memory.
As data is written to tape, the C1 ECC is checked and an interrupt generated if there is an error. The
C1 ECC read from memory is the ECC that is written to tape.
When data is read from tape and stored into memory, C1 ECC is checked.
If the C1 ECC is good, that codeword pair's "Valid" bit is set.
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Otherwise, a pointer to the invalid Codeword Pair is passed to the C1 ECC correction engine.
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If the C1 ECC correction engine can correct the error, then the corrected bytes are writ-
•
ten to memory, and the Valid bit is set.
Otherwise, the Valid bit is left cleared.
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As data is read from memory to the Data Processor for decompression, the C1 ECC is again
checked and an interrupt generated if it is not correct.
C2 ECC
C2 ECC involves three distinct operations:
1. Encoding: Generating C2 ECC bytes from data bytes (performed by ECC co-processor hard-
ware)
Decoding: Generating ECC syndromes from data and ECC bytes, testing for all-zeroes (per-
2.
formed by ECC co-processor hardware)
3. Correction: Generating corrected data from syndromes.
The correction depends on the number and types of errors involved:
For one known C1 codeword pair in error in a sub-data set (C2 codeword), the operation is
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performed by the ECC co-processor hardware.
For two or more known C1 codeword pairs in error, the matrix is computed by firmware and
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the correction is performed by hardware.
For one or more unknown C1 codeword pairs, syndromes are generated by hardware, error
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location is computed by firmware, the matrix is computed by firmware and the correction is
performed by hardware.
Data Integrity
32